UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 75

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.3 Instruction Address Addressing
usually automatically incremented by the number of bytes of the instruction to be fetched (by 1 per byte) every time
an instruction is executed. When an instruction that causes program execution to branch is performed, the address
information of the branch destination is set to the PC by means of the following addressing (for details of each
instruction, refer to 78K/0 Series User’s Manual Instructions (U12326E)).
3.3.1 Relative addressing
An instruction address is determined by the contents of the program counter (PC). The contents of the PC are
[Function]
[Operation]
The 8-bit immediate data (displacement value: jdisp8) of the instruction code is added to the first address of the
next instruction, the resultant sum is transferred to the program counter (PC), and program execution branches.
The displacement value is treated as signed 2’s complement data (–128 to +127), and bit 7 serves as a sign bit.
In other words, relative addressing consists of relative branching from the first address of the following instruction
to the –128 to +127 range.
This addressing is used when the “BR $addr16” instruction or conditional branch instruction is executed.
PC
When S = 0, all bits of
When S = 1, all bits of
15
15
15
are 0.
are 1.
CHAPTER 3 CPU ARCHITECTURE
8
PC
+
7
S
User’s Manual U13029EJ7V1UD
6
jdisp8
0
0
0
...
PC holds first address of instruction
next to BR instruction.
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