UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 302

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UPD78F0988AGC-8BS

Manufacturer Part Number
UPD78F0988AGC-8BS
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0988AGC-8BS

Lead Free Status / Rohs Status
Supplier Unconfirmed
300
Maskable interrupt request
RESET input
: don’t care
(b) Releasing by RESET input
Releasing Source
If the RESET signal is input, the STOP mode is released. The reset operation is performed after the
oscillation stabilization time has elapsed.
Remarks 1. f
RESET
signal
Clock
2. The parenthesized values apply to operation at f
Operation
Oscillation
mode
X
: System clock oscillation frequency
instruction
Figure 16-5. Releasing STOP Mode by RESET Input
Table 16-4. Operation After Release of STOP Mode
STOP
MK
STOP mode
0
0
0
0
0
1
CHAPTER 16 STANDBY FUNCTION
User’s Manual U13029EJ7V1UD
Oscillation
stops
PR
0
0
1
1
1
IE
period
0
1
0
1
Reset
ISP
1
0
1
(2
17
stabilization
wait status
Oscillation
/f
X
Wait
: 10.9 ms)
X
Executes next address instruction.
Executes interrupt servicing.
Executes next address instruction.
Executes interrupt servicing.
Retains STOP mode.
Executes reset processing.
= 12 MHz.
Oscillation
Operation
Operation
mode

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