UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 353

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Bit
manipulation
Call/return
Instruction
Group
Notes 1. When the internal high-speed RAM area is accessed or when an instruction that does not access data
Remarks 1. One clock of an instruction is equal to one CPU clock (f
2. When an area other than the internal high-speed RAM area is accessed
Mnemonic
SET1
CLR1
SET1
CLR1
NOT1
CALL
CALLF
CALLT
BRK
RET
RETI
RETB
2. The number of clocks shown is when the program is stored in the internal ROM area.
3. n indicates the number of wait states when the external memory expansion area is read.
4. m indicates the number of wait states when the external memory expansion area is written.
is executed
register (PCC).
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
!addr16
!addr11
[addr5]
Operand
CHAPTER 19 INSTRUCTION SET
User’s Manual U13029EJ7V1UD
Byte
2
3
2
2
2
2
3
2
2
2
1
1
1
3
2
1
1
1
1
1
Note 1 Note 2
4
–
4
–
6
4
–
4
–
6
2
2
2
7
5
6
6
6
6
6
Clock
8 + n + m
8 + n + m
6
8
–
6
6
8
–
6
–
–
–
–
–
–
–
–
–
–
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
CY
CY
CY
(SP – 1)
PC
(SP – 1)
PC
SP
(SP – 1)
PC
PC
SP
(SP – 1)
(SP – 3)
PC
PC
SP
PC
PSW
NMIS
PC
PSW
15-11
H
L
L
H
H
H
SP – 2
SP – 2
SP + 2
1
0
CY
addr16, SP
CPU
(00000000, addr5),
(003EH), SP
(00000000, addr5 + 1),
(SP + 1), PC
(SP + 1), PC
(SP + 1), PC
1
0
(SP + 2), SP
(SP + 2), SP
1
0
0
00001, PC
) selected by the processor clock control
1
0
(PC + 3)
(PC + 2)
(PC + 1)
1
0
PSW, (SP – 2)
(PC + 1)
1
0
Operation
H
H
H
, (SP – 2)
, (SP – 2)
, (SP – 2)
L
L
L
L
10-0
, PC
SP – 2
SP – 3, IE
(SP),
(SP),
SP + 3,
(SP),
SP + 3
H
addr11,
(PC + 1)
(003FH),
(PC + 3)
(PC + 2)
(PC + 1)
0
H
,
L
L
L
,
,
,
R
R
Z AC CY
Flag
R
R
351
R
R
1
0