UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 330

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UPD78F0988AGC-8BS

Manufacturer Part Number
UPD78F0988AGC-8BS
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0988AGC-8BS

Lead Free Status / Rohs Status
Supplier Unconfirmed
18.4.4 CPU resources
18.4.5 Entry RAM area
328
The CPU resources used during self write are as follows.
• Register bank: BANK3 (8 bytes)
• Stack area: Maximum 16 bytes
• Write data storage area: 1 to 256 bytes
• Entry RAM area: 32 bytes
• Status flag
A description of the entry RAM area is shown in Table 18-6.
Example When the value of the HL register of register bank 3 is 0FD00H
setting error
Parameter
B register: Status flag
C register: Function number
HL register: Entry RAM area starting address
RAM area used by the self-write subroutines.
Can be specified by the user using the HL register.
7
0FD00H: Status
0FD02H: Flash memory start address
0FD06H: Number of bytes written in flash memory
·
·
6
Offset Value
+11 to +13
+14 and +15 Write data storage buffer starting address (2 bytes)
+16 and +17 Total number of blocks and areas (2 bytes)
+2 and +3
+4 and +5
+8 to +10
+18
+0
+1
+6
+7
: .
5
Reserved area (1 byte)
Reserved area (1 byte)
Flash memory start address (2 bytes)
Reserved area (2 bytes)
No. of bytes written in flash memory (1 byte)
Write time data (1 byte)
Erase time data (3 bytes)
Writeback time data (3 bytes)
Reserved area (15 bytes)
Table 18-6. Entry RAM Area
CHAPTER 18
User’s Manual U13029EJ7V1UD
Verify error
4
Description
PD78F0988A
Write error
3
Erase error
2
Blank check
error
1
0

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