TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 129

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Line Timing Generator
The Line Timing Generator (LTG) creates the signals required for the Tx Re-timing FIFO (when Transmit Re-
timing is enabled) and the Tx TOH Generator. In addition, it supplies the timing information to the Tx Terminal
Port in Datacom Mode. There are two sets of external inputs. The pins TLCI (51.84 MHz clock) and TFRI are
used for Tx Line Timing. In Datacom Mode, pins DRCI and DFRI/DFRI are used for Tx Terminal Port Timing.
DFRI/DFRI is active High for parallel mode, and active Low for serial mode. The use of TFRI and/or DFRI/DFRI
is optional. If they are not used the start of the frame output at the Tx Line Port (TFRI) and the Tx Terminal
Port, in Datacom Mode, (DFRI/DFRI) will be arbitrary. If TFRI and/or DFRI/DFRI are not used the controls
TFRIEN (CR12; 1FC[H], Bit 2) and/or DFRIEN (CR12; 1FC[H], Bit 1) should be set to "0" to prevent alarm gen-
eration. Loss Of Tx Reference is reported as LOTR (SR5; 1E8/9/C[H], Bit 1). This alarm is for clock and frame
of both reference sets.
In Datacom Mode, the Tx Terminal Port clock and control signals (TTCI/O, TPCI/O, TSYNI/O and TSPEI/O are
outputs generated from DRCI and DFRI/DFRI. The Pin MBEI and the controls PARA and DETSEL (CR10;
1FA[H], Bit 2) select 51.84, 6.48, or 19.44 MHz reference sets as shown in Table 3. The Generated Frame will
always track the Reference Frame. As long as the clock input is valid, loss of DFRI/DFRI does not impair the
output at the Tx Terminal Port. The Frame alignment prior to the framing pulse loss will be maintained. Any
DFRI/DFRI pulse that varies from the previous position will be reported as a Datacom Reference Change Of
Frame Alignment - DRCOFA (SR5; 1E8/9/C[H], Bit 2). If DFRI/DFRI is not present then the generated frame
alignment will be arbitrary
.
The timing source for the Tx Line may be either the external references TLCI and TFRI, DRCI and DFRI in
Pin MBEI
Pin MBEI
High
High
High
High
High
High
Low
Low
Proprietary TranSwitch Corporation Information for use Solely by its Customers
RCLK
PARA
0
1
1
0
1
1
-
-
RETSEL
DETSEL
0
1
0
1
-
-
-
-
Table 3. Datacom Mode Timing Selection
Timing Mode
External Rx
Line Timing
External Rx
External Rx
Table 2. Rx Timing Selection
DRCI MHz
Timing
Timing
Timing
19.44
51.84
51.84
6.48
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DATA SHEET
Frame Input
RXCK 51.84
Clock Input
RRCI 19.44
RRCI 51.84
RRCI 6.48
DFRI
DFRI
DFRI
DFRI
MHz
MHz
MHz
MHz
19.44 Mbyte/s Parallel
Serial
6.48 Mbyte/s Parallel
6.48 Mbyte/s Parallel
Frame Input
RXFR
RRFI
RRFI
RRFI
Tx Terminal Port Mode
19.44 Mbyte/s Parallel
1. Serial
2. 6.48 Mbyte/s Par-
allel
6.48 Mbyte/s Parallel
1. Serial
2. 6.48 Mbyte/s Par-
allel
Rx Terminal Output
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1