TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 153

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Rx TOH Alarms
Two Transport Alarms are extracted from Bits 6-8 of the K2 Byte. Line AIS is reported as RAIS-L (SR0;
0F0/1/4[H], Bit 4) and is detected as a "111" condition. Line RDI is reported as RRDI-L (SR1; 0F2/3/5[H], Bit 3)
and is detected as "110". A Received APS Alarm - RAPS (SR1; 0F2/3/5[H], Bit 2) is derived from a consistency
check of the K1 and K2 Bytes. Additionally, a Received Line E1 Alarm - RLE1 (SR4; 1F2/3/5[H], Bit 4) is
extracted from the E1 Byte, when so optioned. RLE1 detection assumes that some upstream entity has
detected an AIS condition and uses the E1 Byte for in-band communication of the condition. Use of the Rx Line
E1 Byte in this manner is enabled when RE2A (CR11; 1FB[H], Bit 3) is set to "1".
Rx C1/J0 Processing
In addition to the debouncing described earlier, optional processing of the C1 Byte can be performed to sup-
port J0 Functionality (Section Trace). Four forms of J0 Processing are supported. They consist of:
J0 Processing is controlled by bits J0EN0 and J0EN1 (CR18; 1DC[H], Bits 3 and 4)
One Byte Processing consists of comparing the content of the received C1 Byte to the value in the J0 EXPECT
RAM Location (067[H]). Mismatch results in an alarm which is reported to the µPro as J0MIS (SR6;
0EA/B/D[H], Bit 3).
When multiple byte J0 options are selected no mismatch detection is performed by hardware. It is assumed
that this will be performed by software. Received, multiple byte J0 messages are stored in a 64-byte RAM seg-
ment. This means that there will be four copies of a 16-byte message or one copy of a 64-byte message. The
RAM Segment is accessible by the µPro through addresses 080[H] - 0BF[H]. This address space is shared by
the 64-byte memory segment used to store the received J1 Bytes. The control J0RWEN (CR18; 1DC[H], Bit 7)
is used to control the address space. When set to "1", the J0 Bytes are available.
Rx B1 Processing
B1 Errors are accumulated in an eight or sixteen-bit saturating counter designated Rx B1 Error Count (046[H]),
which is readable by the µPro. The selection of Eight-Bit Mode or Sixteen-Bit Mode is controlled by CNT16EN
(CR3; 0FB[H], Bit 2). CNT16EN = "0" defines Eight-Bit Mode. Counter overflow is indicated by RB1COF (SR7;
0F6[H], Bit 5). The manner in which B1 Byte errors are determined is dependent on the setting of STS1. When
set to "0" the incoming B1 Byte may contain from zero to eight ones. Each "1" represents an error detected by
an upstream device. The number of bits at the "1" Level is accumulated. If STS1 = "1" the B1 Byte, extracted
after unscrambling, is compared to a B1 value calculated before unscrambling. The calculation is Even Parity,
independently performed, in parallel, over the eight bit positions. The errors (up to eight per frame) are accu-
mulated.
Rx B2 Processing
B2 Errors are readable by the µPro at the location Rx B2 Error Count (047[H]) and counter overflow is indicated
by RB2COF (SR7; 0F6[H], Bit 6). They are accumulated in the same manner as with the B1 Byte, with STS1 =
“1”, except that the B2 calculation is performed after unscrambling and excludes the nine Section Bytes. The
number of received errors (including zero) is made available to the Transmit Side and to the Ring Port for use
as a Line FEBE.
1. One Byte J0 Hardware Compare
2. Reception and Storage of a 16-Byte message
3. Reception and Storage of a 64-Byte message with ASCII CR/LF alignment
4. Reception and Storage of a 64-Byte message without ASCII CR/LF alignment
Proprietary TranSwitch Corporation Information for use Solely by its Customers
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DATA SHEET
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1