TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 170

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Notes:
1. Selection options are affected by the generation of Path Idle. See "Idle Insertion" below.
2. Only if H4INT, TPFEBEEN, TPRDIEN, TPRDIPD, TPRDICD and TPRDISD = "0". If H4INT, TPFEBEEN, TPRDIEN,
3. In SPE-only Mode, Datacom Mode, or SONET Mode with C1J1EN = "1" and if H4INT = "1", and RTLOOP = "0" then the
The selected B3 Byte will be Exclusive-OR gated with the Tx B3 Error Mask (1D0[H]). If B3 is not internally cal-
culated, then the number of errors generated will be doubled. TRERR (CR11; 1FB[H], Bit 6) is used to enable
an automatic reset to all "0" of the B3 Error Mask. When set to "1" the B3 Error Mask will be reset after one
frame. A value of "0" disables the automatic reset feature.
Tx Path FEBE Insertion
The Path FEBE (FEBE-P) function is enabled by TPFEBEEN. When activated, Bits 1 through 4 of the G1 Byte
selected above are overwritten with a value of "0000" - "1000". If RING (CR11; 1FB[H], Bit 4) = "0" the number
of received B3 Errors is the source for the FEBE-P Value. When RING = "1" the FEBE-P Value is supplied by
the Ring Port. Since the received and transmitted SPE Rates may differ, an accumulation mechanism is
employed to ensure that the FEBE-P Count returned will equal the B3 Errors received.
Byte(s)
TPRDIPD, TPRDICD or TPRDISD = "1" then Calculated Value will be used.
two LSBs will be overwritten by the Internal H4 Counter value.
G1
B3
C2
H4
F2
Z3
Z4
Z5
J1
1
1
1
1
1
1
1
1
1
Control Bit
TXH4INS
TG1EXT
TC2EXT
TJ1EXT
TF2EXT
TZ3EXT
TZ4EXT
TZ5EXT
Proprietary TranSwitch Corporation Information for use Solely by its Customers
-
Location CR#;
CR13; 1FD, 7
CR13; 1FD, 6
CR13; 1FD, 5
CR13; 1FD, 4
CR13; 1FD, 3
CR13; 1FD, 2
CR13; 1FD, 1
CR13; 1FD, 0
Reg, Bit
-
Table 23. Tx Line POH Options
Tx Terminal C2 Byte
Tx Terminal G1 Byte
Tx Terminal H4 Byte
Tx Terminal F2 Byte
Tx Terminal Z3 Byte
Tx Terminal Z4 Byte
Tx Terminal Z5 Byte
Tx Terminal J1 Byte
Tx Terminal B3
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TPATH
Byte
DATA SHEET
2
Tx Terminal H4
µPro C2 Bytes
µPro G1 Bytes
µPro F2 Bytes
µPro Z3 Bytes
µPro Z4 Bytes
µPro Z5 Bytes
µPro J1 Bytes
Control="0"
Byte
3
Calculated Value
TPATH="1"
Tx POH Port C2 Bytes
Tx POH Port F2 Bytes
Tx POH Port Z3 Bytes
Tx POH Port Z4 Bytes
Tx POH Port Z5 Bytes
Tx POH Port J1 Bytes
Tx POH Port G1
µPro H4 Bytes
Control="1"
Bytes
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1
3