TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 165

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Proprietary TranSwitch Corporation Information for use Solely by its Customers
PHAST-1
DATA SHEET
TXC-06101
Input Frame Delineation
In all SONET Modes there are two methodologies for determining the start of the Frame and the SPE: Framing
Mode and C1J1 Mode. The selection is determined by C1J1EN. The setting of C1J1EN is disregarded in SPE-
only and Datacom Modes.
Framing Mode
In this mode of operation (C1J1EN = "0") TSYNI/O and TSPEI/O are disregarded. The A1/A2 and H1/H2 Bytes
incoming to the Tx Terminal Port are used to determine Frame and SPE alignment. In Parallel modes the
F6[H], 28[H] Framing Pattern (A1 and A2) must occur on byte boundaries. When the 19.44 Mbyte/s format is
employed, Framing is found and checked on the First F6[H] and 28[H] bytes occurring in the same numbered
slot. The Framing Circuitry detects Framing Errors - TFE (SR5; 1E8/9/C[H], Bit 6), Severely Errored Frame -
TSEF (SR2; 1F0/1/4[H], Bit 1) and Loss of Frame - TLOF (SR2; 1F0/1/4[H], Bit 2).
Line AIS detection is optionally performed using the K2 Byte. This function is enabled by DISTLAIS = "0"
(CR12; 1FC[H], Bit 5) and the alarm reported as TAIS-L (SR2; 1F0/1/4[H], Bit 4). If bits 6, 7, and 8 of the K2
Byte are indeterminate, then control bit DISTLAIS must be set to "1" to inhibit the TAIS-L Alarm.
Pointer Processing results in the generation of the following alarms: Loss of Pointer - TLOP (SR2; 1F0/1/4[H],
Bit 3), New Pointer - TNPTR (SR2; 1F0/1/4[H], Bit 6), Concatenated Pointer - TCPTR (SR5; 1E8/9/C[H], Bit 5),
Path AIS - TAIS-P (SR2; 1F0/1/4[H], Bit 5). TCPTR is not a true alarm. Detection of a Concatenation Indication
will always result in the declaration of TLOP. TCPTR serves as an indication of an illegal condition that has
caused the TLOP Alarm. Pointer Increments and Decrements are accumulated in four-bit counters which are
accessed at the RAM Location designated Tx Inc/Dec Count (145[H]). Bits 0 through 3 indicate the Decrement
Count. Bits 4 through 7 are for Increments. Overflow of either counter is indicated by TPMOVOF (SR8; 1F6[H],
Bit 4).
C1J1 Mode
Under this condition (C1J1EN = "1") the TSYNI/O and TSPEI/O signals are enabled. The information content
of the A1, A2, H1 and H2, Bytes is disregarded. Framing and Pointer Tracking are not performed and the asso-
ciated alarms are inhibited. If bits 6,7 and 8 of the K2 Byte are indeterminate then DISTLAIS must be set to "1"
to inhibit the TAIS-L Alarm.
In SONET modes, TSYNI/O is an input and contains C1, J1 and optional V1 Information. The relationships of
TSPEI/O and TSYNI/O to the input data and clock are shown in Figures 55,
57
and 60. The V1 portion of
TSYNI/O is enabled when the control H4INT = "1". Under these conditions the V1 pulse is used to synchronize
a two-bit, modulo four counter which creates the information for the H4 Byte that is sent to the Tx Line.
In Datacom modes, TSYNI/O is an output which contains C1, J1 and optional V1 Information. The relation-
ships of the TSPEI/O and TSYNI/O outputs to the input data are shown in Figures 62,
64
and 66. The V1 por-
tion of TSYNI/O is enabled when the control H4INT = "1". Under these conditions the external Datacom
Reference Signal (DFRI or DFRI) must occur once every 500 µs. When the reference signal is active, the two-
bit modulo 4 counter is set such that the H4 Byte sent to the Tx Line contains "00" and the V1 Portion of
TSYNI/O will be output. If DFRI/DFRI is not supplied when H4INT = "1", the two-bit counter will still count, pro-
ducing the V1 indicator at TSYNI/O and inserting its value in the two LSB’s of H4, although its initial value will
be arbitrary. If DFRI/DFRI is lost the operation will not be disturbed and the same V1 alignment will be main-
tained.
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TXC-06101-MB
Ed. 3, April 2001