TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 156

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Rx Line FEBE Processing
Processing of FEBE-L consists of recording the number of errors received in Z2 Byte Bits 5 - 8. Line FEBE
Errors are accumulated in an eight or sixteen-bit saturating counter designated FEBE-L Count (040[H]).
Counter overflow is indicated by RLFEBEOF (SR7; 0F6[H], Bit 3).
Rx Pointer Tracking
The H1 and H2 Bytes are used to determine the Received J1 Position and are interpreted for:
RCPTR is not an alarm per se. Reception of a Concatenation Indication will always result in the declaration of
RLOP . RCPTR serves as an indication of an illegal condition that has caused the RLOP Alarm. Pointer Incre-
ments and Decrements are accumulated in four-bit Counters which are accessed at the RAM Location desig-
nated Rx Inc Count/Dec Count (045[H]). Bits 0 through 3 indicate the Decrement Count. Bits 4 through 7 are
for Increments. In addition, both Pointer Increments and Decrements are accumulated in an eight-bit counter
which can be read by the µPro in the RXPJCNT Location (044[H]). RPMOVOF (SR7; 0F6[H], Bit 2) is the over-
flow indication for the Inc and Dec counters and RPJOF (SR7; 0F6[H], Bit 1) indicates overflow of RXPJCNT.
RX POH PROCESSING
All received POH processing is performed by the Rx POH Processor Block. All Received POH Bytes are writ-
ten into RAM for access by the µPro. They are also externally available at the Rx POH Port. Selected bytes are
debounced. Further processing is executed for alarm extraction and for performance monitoring.
Received POH Byte Locations
The Memory Locations for the Received POH Bytes are given in Table 12. The locations 080[H] - 0BF[H] are
shared with the J0 bytes and access is controlled by J0RWEN. J1 Byte storage is controlled by J1SYNCEN
(CR6; 0FE[H], Bit 4). When set to "0" the J1 Bytes are stored in the 64-Byte Segment, in rotating fashion, with
no specific starting point. If J1SYNCEN = "1" reception of ASCII characters CR and LF, in sequence, will cause
the next J1 Byte to be written at address 080[H], with subsequent bytes being stored in succeeding locations.
1. New Pointer - RNPTR (SR0; 0F0/1/4[H], Bit 6)
2. Concatenation - RCPTR (SR3; 0E8/9/C[H], Bit 3)
3. Loss of Pointer - RLOP (SR0; 0F0/1/4[H], Bit 3)
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Table 12. Received POH Locations
Byte
C2
G1
H4
B3
F2
Z3
Z4
Z5
J1
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DATA SHEET
080[H] - 0BF[H]
4. Path AIS - RAIS-P (SR0; 0F0/1/4[H], Bit 5)
5. Pointer Increment
6. Pointer Decrement
Location
0C0[H]
0C1[H]
0C2[H]
0C3[H]
0C4[H]
0C5[H]
0C6[H]
0C7[H]
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1