TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 184

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Proprietary TranSwitch Corporation Information for use Solely by its Customers
PHAST-1
DATA SHEET
TXC-06101
TEST AND DIAGNOSTICS
For testing and diagnostic purposes the PHAST-1 provides Loopbacks (previously discussed), Output Disable
capability and Boundary Scan.
Output Disable
The pin TEST is a control that when taken Low, with RST held Low, will force all output and bidirectional pins to
a high impedance state. TEST at the Low Level by itself invokes a TXC Device Test Mode. For normal opera-
tion TEST must be at the High Level.
Boundary Scan
Introduction
The IEEE 1149.1 Standard defines the requirements of a boundary scan architecture that has been specified
by the IEEE Joint Test Action Group (JTAG). Boundary scan is a specialized scan architecture that provides
observability and controllability for the interface pins of the device. The Test Access Port block, which imple-
ments the boundary scan functions, consists of a Test Access Port (TAP) controller, instruction and test data
registers, and a boundary scan register path bordering the input and output pins, as illustrated in Figure 79.
The boundary scan test bus interface consists of four input signals (i.e., the Test Clock (TCKI), Test Mode
Select (TMSI), Test Data Input (TDI) and Test Reset (TRESI) input signals) and a Test Data Output (TDO) out-
put signal. A brief description of boundary scan operation is provided below; further information is available in
the IEEE Standard document.
The TAP controller receives external control information via a Test Clock (TCKI) signal, a Test Mode Select
(TMSI) signal, and a Test Reset (TRESI) signal, and it sends control signals to the internal scan paths. The
scan path architecture consists of a three-bit serial instruction register and two or more serial test data regis-
ters. The instruction and data registers are connected in parallel between the serial Test Data Input (TDI) and
Test Data Output (TDO) signals. The Test Data Input (TDI) signal is routed to both the instruction and test data
registers and is used to transfer serial data into a register during a scan operation. The Test Data Output (TDO)
is selected to send data from either register during a scan operation.
When boundary scan testing is not being performed, the boundary scan register is transparent, allowing the
input and output signals at the device pins to pass to and from the PHAST-1 device’s internal logic, as illus-
trated in Figure 79. During boundary scan testing, the boundary scan register disables the normal flow of input
and output signals to allow the device to be controlled and observed via scan operations. A timing diagram for
the boundary scan feature is provided in Figure 59.
Boundary Scan Support
The maximum frequency the PHAST-1 device will support for boundary scan is 10 MHz. The PHAST-1 device
performs the following boundary scan test instructions (ID commands and ID Register are not supported):
- EXTEST (000)
-SAMPLE/PRELOAD (010)
-BYPASS (111)
It should be noted that the Capture - IR State (INSTRUCTION_CAPTURE attribute of BSDL) is 011.
EXTEST Test Instruction:
One of the required boundary scan tests is the external boundary test (EXTEST) instruction. When this
instruction is shifted in, the PHAST-1 device is forced into an off-line test mode. While in this test mode, the test
bus can shift data through the boundary scan registers to control the external PHAST-1 input and output leads.
SAMPLE/PRELOAD Test Instruction:
When the SAMPLE/PRELOAD instruction is shifted in, the PHAST-1 device remains fully operational. While in
this test mode, PHAST-1 input data, and data destined for device outputs, can be captured and shifted out for
inspection. The data is captured in response to control signals sent to the TAP controller.
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TXC-06101-MB
Ed. 3, April 2001