TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 163

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

The remaining POH Bytes may be selected from the Rx Line or the Insert Locations given in Table 19. All loca-
tions except 0C8[H] are written by the µPro. The B3 Location is the calculated BIP-8. The Calculation is Even
Parity, independently performed, in parallel, over the eight bit positions of the outgoing SPE Bytes. The value
calculated for Frame n is placed in the B3 Byte of Frame n+1. Prior to output, the B3 value is Exclusive-OR
gated with the B3 Error Mask. This is Location 0D0 [H].
Selection is controlled by RPATH (CR0; 0F8[H], Bit 3). A Setting of "0" selects the Bytes from the Rx Line.
When set to "1" the Insert POH Bytes will appear at the Rx Terminal Port.
Rx Terminal Alarm Generation
Line AIS insertion consists of forcing all Line Overhead Bytes (H1, H2, ..., Z2, E2) and all SPE Bytes to "1".
AIS-L insertion is directly controlled by the µPro via the command SRLAIS (CR4; 0FC[H], Bit 7). In addition
AIS-L may, as an option, be automatically inserted upon certain Receive Side anomalies. Enabling of auto-
matic insertion is controlled by RRAIS (CR1; 0F9[H], Bit 3) and LTE (CR1; 0F9[H], Bit 2). The Inclusion of
B2EBER is enabled by B2XAIS (CR4; 0FC[H], Bit 6) and the Inclusion of J0MIS is enabled by J0MLAIS (CR18;
1DC[H], Bit 5). When re-timing is employed, the insertion of AIS-L will terminate with the sending of a valid
pointer with the NDF Bits active ("1001") for one frame. Subsequent pointer values are transmitted with an
inactive NDF ("0110") indication. If re-timing is disabled, termination will consist of removing the "1" forcing
function. If the conditions are such that a Line AIS will be inserted (if enabled by RRAIS) it will be indicated by
RLAISC (SR8; 1F6[H], Bit 2).
Path AIS insertion consists of setting the H1, H2 and H3 Bytes and all SPE Bytes to "1". AIS-P insertion is
directly controlled by the µPro via the command SRPAIS (CR4; 0FC[H], Bit 5). PAIS insertion will also occur on
Receive FIFO underflow or overflow, if the automatic FIFO recovery option is set. In addition, AIS-P may, as an
option, be automatically inserted upon certain received alarms. Five of the conditions for autonomous insertion
are options. They are B3EBER, RLOM, C2MIS, C2UNEQ and RLE1. They are enabled, respectively, by the
controls: B3XPAIS, RLOMPAIS, C2MPAIS, C2UPAIS and RLEAIS (CR4; 0FC[H], Bits 4, 3, 2, 1, and 0).
Enabling of automatic insertion is controlled by RRAIS, LTE and PTE (CR9; 1F9[H], Bit 2). If re-timing is
enabled the insertion of AIS-P will terminate with the sending of a valid pointer with the NDF Bits active
("1001") for one frame. Subsequent pointer values are transmitted with an inactive NDF ("0110") indication.
When re-timing is disabled, termination of AIS-P will consist of removing the "1" forcing function. When the
conditions are such that a Path AIS will be inserted (if enabled by RRAIS) it will be indicated by RPAISC (SR8;
1F6[H], Bit 3).
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Table 19. Terminal Insert POH Locations
Byte
(B3)
C2
G1
F2
Z3
Z4
Z5
- 163 of 196 -
DATA SHEET
Location
0CD[H]
0CA[H]
0CB[H]
0CE[H]
0CF[H]
0C8[H]
0C9[H]
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1