SAB80C535N Infineon Technologies, SAB80C535N Datasheet - Page 34

• Manufacturer Part Number: SAB80C535N
• Manufacturer: Infineon Technologies

Specifications of SAB80C535N

• Cpu Family: C500
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 12MHz
• Interface Type: Serial
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 256Byte
• # I/os (max): 48
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

When idle mode is used, pin PE must be held on low level. The idle mode is then entered by
two consecutive instructions. The first instruction sets the flag bit IDLE (PCON.0) and must not
set bit IDLS (PCON.5), the following instruction sets the start bit IDLS (PCON.5) and must not
set bit IDLE (PCON.0). The hardware ensures that a concurrent setting of both bits, IDLE and
IDLS, does not initiate the idle mode. Bits IDLE and IDLS will automatically be cleared after
being set. If one of these register bits is read the value that appears is 0 (see table 4). This
double instruction is implemented to minimize the chance of an unintentional entering of the
idle mode which would leave the watchdog timer’s task of system protection without effect.
Note that PCON is not a bit-addressable register, so the above mentioned sequence for
entering the idle mode is obtained by byte-handling instructions, as shown in the following
example:
ORL
ORL
The instruction that sets bit IDLS is the last instruction executed before going into idle mode.
There are two ways to terminate the idle mode:
– The idle mode can be terminated by activating any enable interrupt. This interrupt will
– The other way to terminate the idle mode, is a hardware reset. Since the oscillator
Power-Down Mode
In the power-down mode, the on-chip oscillator is stopped. Therefore all functions are stopped;
only the contents of the on-chip RAM and the SFR's are maintained.The port pins controlled by
their port latches output the values that are held by their SFR's.
The port pins which serve the alternate output functions show the values they had at the end
of the last cycle of the instruction which initiated the power-down mode; when the clockout
signal (CLKOUT, P1.6) is enabled, it will stop at low level. ALE and PSEN hold at logic low
level (see table 5).
To enter the power-down mode the pin PE must be on low level. The power-down mode then
is entered by two consecutive instructions. The first instruction has to set the flag bit PDE
(PCON.1) and must not set bit PDS (PCON.6), the following instruction has to set the start bit
PDS (PCON.6) and must not set bit PDE (PCON.1). The hardware ensures that a concurrent
setting of both bits, PDE and PDS, does not initiate the power-down mode. Bits PDE and PDS
will automatically be cleared after having been set and the value shown by reading one of these
bits is always 0 (see table 4). This double instruction is implemented to minimize the chance of
unintentionally entering the power-down mode which could possibly "freeze" the chip's activity
in an undesired status.
Semiconductor Group
be serviced and normally the instruction to be executed following the RETI instruction
will be the one following the instruction that sets the bit IDLS.
is still running, the hardware reset must be held active only for two machine cycles
for a complete reset.
PCON,#00000001
PCON,#00100000
B
B
;Set bit IDLE, bit IDLS must not be set
;
Set bit IDLS, bit IDLE must not be set
33
SAB 80C515/80C535