H27U8G8T2BTR-BC HYNIX SEMICONDUCTOR, H27U8G8T2BTR-BC Datasheet - Page 10

• Manufacturer Part Number: H27U8G8T2BTR-BC
• Description: 58T1893
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H27U8G8T2BTR-BC

• Memory Type: Flash - NAND
• Memory Size: 8192Mbit
• Memory Configuration: 1024M X 8
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes

3. DEVICE OPERATION
command register along with five address cycles. After a 1st page read operation, device remains in read mode, that is to
say that a 2nd page read can start just by inputting 5 address cycles and read confirm command; in other words 00h com-
mand cycle is not necessary. Also after power up device is in read mode, so 00h command cycle is not necessary to start
a read operation. Any operation different from read or random data output causes the device to exit read mode.
the page address is changed. The 4,224 bytes of data within the selected page are transferred to the data registers in less
than 60us (tR). The system controller may detect the completion of this data transfer (tR) by analyzing the output of R/B
pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially
pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected
column address up to the last column address in the page.
command (05h-E0h as in Figure 13)
data output command.
planes, a read of two pages (one for each plane) is enabled by activating two sets of 4,224 byte page registers(one for
each plane). Multi-Plane Page Read is initiated by repeating command 60h followed by three address cycle twice and then
by entering 30h confirm command. In this case only the same page of the same block can be selected from each plane.
registers in less than 60us(tR). The system controller can detect the completion of data transfer (tR) by monitoring the
output of R/B pin.
Five Address Cycles (all 00h), command 05h with two column address and finally E0h and then toggling RE: if two column
address is 00h, then the read-out starts from the beginning of the page, otherwise data-out will start from selected column
for random data-out.
except A20=1), command 05h with two column address and finally E0h and then toggling RE : if two column address is
00h, then the read-out starts from the beginning of the page, otherwise data-out will start from selected column for random
data out.
Five Address Cycles, command 05h with two column address and finally E0h: in 5 address cycles A20=0 allows random
read in 1st plane page, while A20=1 allows random read in 2nd plane page (Figure 14).
which has been programmed with Multi-Plane Page Program.
Rev 0.0 / Jul. 2008
3.1 Page Read.
3.2 Multiplane Page Read
Upon initial power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the
Two types of read operations are available: random and serial read in a page. The random read mode is enabled when
The device may output random data in a page instead of the consecutive sequential data by writing random data output
The column address of next data, which is going to be output, may be changed to the address which follows random
Random data output can be operated regardless of how many times it is done in a page.
Check Figure 11, Figure 12 and Figure 13 as a reference.
Multi-Plane Page Read is an extension of Page Read for a single plane. Since the device is equipped with two memory
After Read Confirm command (30h) the 8,448 bytes of data within the selected two pages are transferred into the data
Once the data are loaded into the data registers, the first plane's data must be read out by issuing command 00h with
The second plane's data must be read out using the command sequence command 00h with Five Address Cycles (all 00h
To execute multiple random data-out within the same two pages selected, the command sequence is command 00h with
Restrictions and details for Multi-Plane Page Read are shown in Figure 14. Multi- Plane Read must be used in the block
8 Gbit (1024 M x 8 bit) NAND Flash
H27U8G8T2B Series
Preliminary
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