H27U8G8T2BTR-BC HYNIX SEMICONDUCTOR, H27U8G8T2BTR-BC Datasheet - Page 9

• Manufacturer Part Number: H27U8G8T2BTR-BC
• Description: 58T1893
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H27U8G8T2BTR-BC

• Memory Type: Flash - NAND
• Memory Size: 8192Mbit
• Memory Configuration: 1024M X 8
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes

2. BUS OPERATION
Data Output, Write Protect, and Standby.
affect bus operations.
able low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising edge of
Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See
Figure 5 and Table 12 for details of the timings requirements.
Gbit device, 5 clock cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command
Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts
a modify operation (write/erase) the Write Protect pin must be high. See Figure 6 and Table 12 for details of the timings
requirements. In addition, addresses over the addressable space are disregarded even if the user sets them during com-
mand insertion.
by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable
low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See Figure 7 and Table 12
for details of the timings requirements.
status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write Enable
High, Address Latch Enable low, and Command Latch Enable low. See Figure 8, 9, 10 and Table 12 for details of the timings
requirements.
start and the content of the memory is not altered or it is interrupted without guarantee about memory content not being
altered. Write Protect pin is not latched by Write Enable, so as to ensure protection even during power up phases.
holding high, at least for 10us, CE pin.
Rev 0.0 / Jul. 2008
2.1 Command Input.
2.2 Address Input.
2.3 Data Input.
2.4 Data Output.
2.5 Write Protect.
2.6 Standby.
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Typically glitches less than 3 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip En-
Address Input bus operation allows the insertion of the memory address. To insert the 31 bits needed to access the 8
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and timed
Data Output bus operation allows to read data from the memory array and to check the status register content, the lock
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation does not
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced. Stand-by is obtained
8 Gbit (1024 M x 8 bit) NAND Flash
H27U8G8T2B Series
Preliminary
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