RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 243

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RS8234EBGC

Manufacturer Part Number
RS8234EBGC
Description
RS8234EBGC ATM XBR SAR
Manufacturer
Mindspeed Technologies
Datasheet

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Figure 10-1. RS8234—Local Processor Interface
28234-DSH-001-B
NOTE(S):
(1)
(2)
Required to address full 8-MB range. Typically, fewer address lines are used.
Required for non-i960 processors.
RS8234
Data Enable
Chip Select
Address
Control
Status
Clock
Data
10.0 Local Processor Interface
10.1 Overview
The RS8234 integrated circuit can be used in conjunction with an external
processor that performs initialization, link management, monitoring, and control
functions. The local processor interface consists of a “loosely coupled”
architecture where it interfaces to the RS8234 through bidirectional transceivers
and buffers that are controlled by the local processor and the RS8234, as shown in
Figure
SAR shared memory and control registers, while insulating the RS8234 from
processor instruction and data cache fills. This also allows the local processor the
option to control multiple RS8234 and/or physical interface devices.
10-1. This architecture allows the processor access to all of the RS8234
Mindspeed Technologies
/OE
/OE
x17 Buff
x32 Xcvr
Optional
Decode
Logic
(2)
Dir
(1)
10
Clock
Data
Dir
Address
High Address
Control
Status
Local Processor
100074_070
10-1

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