RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 348

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

15.0 Electrical and Mechanical Specifications
15.1 Timing
15.1.4 RS8234 Memory Interface Timing
Memory access times and other timing requirements are specified at three typical implementations of one, two,
and four banks of by_8 SRAM.
organizations while
typical implementations. RS8234 memory interface timing is given in
memory bank organization.
Table 15-5. SRAM Organization Loading Dependencies
Table 15-6. SAR Shared Memory Output Loading Conditions
15-8
LADDR[18:0]
LDATA[31:0]
MWR*
MOE*
MCSx*
MWEx*
NOTE(S):
(1)
(2)
LADDR[18:0]
MOE*
MWR*
LDATA[31:0]
MWE[3:0]*
MCS[3:0]*
NOTE(S):
(1)
(2)
Typical input loading for SRAM is 7 pF. For exact values, consult the SRAM databook.
Only connected to one bank by definition.
In general, the LADDR loading is the most critical parameter, one bank of by_8 SRAM has the same address loading as two
banks of by_16 and 1/2 bank of by_4 SRAM. For example, use the timing from the two banks of by_8 column for four banks
of by_16 SRAM, or one bank of by_4 SRAM.
For by_16 SRAM, the WE* input has the same loading as the address bus and OE*; therefore, 16 loads specified by the four
banks of by_8 is not applicable, since the maximum number of by_16 SRAMs supported is eight.
(1)
(1)
(2)
(1, 2)
(1)
Signal
Signal
(1)
(1)
(1)
Table 15-6
gives the capacitive loading used in the timing specifications given for the three
Table 15-5
4 banks of by_8
by_16 SRAM
SRAM
150
150
Mindspeed Technologies
—
50
50
50
2
1
2
2
2
1
Memory Interface Loading
gives the number of loads per bank for the different SRAM
2 banks of by_8
SRAM
ATM ServiceSAR Plus with xBR Traffic Management
100
100
50
35
35
35
Loads/Bank
by_8 SRAM
(1)
N/A
4
1
4
4
1
Table
™
(1)
15-7. See
by_8 SRAM
1 bank of
50
50
35
25
25
25
Section 9.2
by_4 SRAM
28234-DSH-001-B
N/A
8
1
8
8
2
for details of
Units
pF
pF
pF
pF
pF
pF
RS8234