RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 271

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

28234-DSH-001-B
12.0 ATM Utopia Interface
12.1 Overview of ATM UTOPIA Interface
The ATM UTOPIA interface contains receive and transmit framer interface logic
and receive error generation logic. The ATM UTOPIA interface block also
interfaces with the segmentation and reassembly coprocessors.
segmentation coprocessor and transmits them to the PHY device while inserting a
dummy HEC. The interface also receives 53 octet cells from the PHY device,
removes the HEC, and saves them in a FIFO to be used by the reassembly
coprocessor.
controlling the ATM link interface chip, which carries out all the transmission
convergence and physical media dependent functions defined by the ATM
protocol. The block performs the following functions:
The ATM UTOPIA interface for the RS8234 accepts 52 octet cells from the
The ATM UTOPIA interface is responsible for communicating with and
• Receives and transmits ATM UTOPIA interface logic. The ATM UTOPIA
• Receives cell synchronization logic, which validates cell boundaries in the
• Transmits cell synchronization logic, which converts the 32-bit data read
• Generates and checks odd parity on the octet transmit and receive data
interface accommodates the Mindspeed RS825x framer device, a
UTOPIA-compatible framer or a Mindspeed-conceived slave UTOPIA
interface, and is responsible for converting between these devices and the
internal data interfaces. The Slave UTOPIA interface connects the RS8234
to a cell-switched backplane.
incoming byte stream, strips off the HEC byte from the ATM header, and
formats the remaining 52 bytes into thirteen 32-bit words before passing
them to the incoming cell FIFO. The receive cell synchronization logic
ensures that only complete cells are passed down to the remainder of the
reassembly controller.
from the transmit cell FIFO buffer into an 8-bit (plus parity) stream,
generates appropriate cell delineation pulses for use by the transmit ATM
UTOPIA interface, and inserts the blank HEC byte into the ATM header of
each cell prior to transferring it to the UTOPIA interface.
buses.
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