RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 297

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
0xb8 - ABR Decision Table Lookup Base Register (SCH_ABRBASE)
The SCH_ABRBASE register sets the base address in SAR shared memory for the ABR decision table. This
address is 128-byte aligned, and only the 16 most significant bits of the address are specified in the
SCH_ABRBASE register.
0xbc - ABR Congestion Register (SCH_CNG)
The SCH_CNG register sets each reassembly free buffer queue to a congested or non-congested state for
transmitted reverse RM cells.
28234-DSH-001-B
31-29
27-16
15-0
31-0
Bit
Bit
28
Field
Field
Size
Size
12
16
32
3
1
Reserved
OOR_EN
OOR_INT
SCH_ABRB[15:0]
FBQ_CNG[31:0]
Name
Name
Mindspeed Technologies
Program and read as zero.
Enable ABR out-of-rate Forward RM cell generation.
ABR out-of-rate Forward RM cell interval. A VCC is examined for an
out-of-rate cell every OOR_INT schedule slots.
Base address for the ABR decision table.
Congestion state for each free buffer queue.
™
Description
Description
13.0 RS8234 Registers
13.4 Scheduler Registers
13-15