RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 306

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

13.0 RS8234 Registers
13.6 Counters and Status Registers
Host Interrupt Status Registers
These two registers contain all interruptible status bits for the host processor. The corresponding interrupt
enables are located in the HOST_IMASKx registers. Status types are defined as:
13-24
0x1c0 - Host Processor Interrupt Status Register 0 (HOST_ISTAT0)
L
E
DE
NOTE:
25-24
21-19
31–0
Bit
Bit
31
30
29
28
27
26
23
22
18
Only host reads will reset the status bits in the HOST_ISTAT0 register.
Field
Field
Size
Size
Level-sensitive status—A logic one on the status bit will cause an interrupt when enabled by the
corresponding IMASK bit. Reading the status does not clear the status or interrupt. The source
of the condition causing the status must be cleared before the status or interrupt is cleared.
Event driven status—A 0 ->1 transition on the status bit causes an interrupt when enabled.
Reading the status register clears the status bit and the interrupt.
Dual Event status—A 0 -> 1 and 1 -> 0 transition on the status bit can be enabled to cause an
interrupt. Reading the status register clears the status bit and the interrupt.
32
1
1
1
1
1
1
2
1
1
3
1
LP_MBOX[31:0]
Type
—
—
—
—
—
L
L
E
E
L
E
Name
PFAIL
PHY_INTR
Reserved
HOST_MBOX_
WRITTEN
LP_MBOX_READ
Reserved
Reserved
Reserved
HSTAT1
Reserved
GFC_LINK
Mindspeed Technologies
Name
Local processor mailbox register. Messages flow from host processor to
local processor.
ATM ServiceSAR Plus with xBR Traffic Management
Reflects inverted state of processor PFAIL* input.
In standalone operation, this bit reflects the inverted state
of the PDAEN* input. PHY_INTR can be connected to a
PHY interrupt source.
Read as zero.
This bit is set upon a write to the HOST_MBOX register
by the local processor, and cleared by a read of the
HOST_MBOX register.
This bit is set upon the read of the LP_MBOX register by
the local processor.
Read as zero.
Read as zero.
Read as zero. Reserved for future status page expansion.
This bit is set when any bit in HOST_ISTAT1 is set.
Read as zero.
Set when three consecutive received cells have GFC
SET_A, SET_B, or HALT bits set.
™
Description
Description
28234-DSH-001-B
RS8234