RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 266

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

11.0 PCI Bus Interface
11.6 PCI Bus Slave Logic
11-6
11.6 PCI Bus Slave Logic
The PCI slave logic permits the host CPU on the PCI bus to access and modify
RS8234 resources (the external SAR shared memory, internal memory, and
internal registers). Because the control processor also has access to these
resources, the PCI slave logic must arbitrate for access prior to performing any
read or write transaction. The slave logic also contains the PCI configuration
registers. These registers control the PCI slave and master interfaces, and can be
read or written at any time by the PCI host. The slave logic implements the
synchronizers required for rate-matching between the PCI bus clock and the
internal RS8234 system clock. Also, small FIFOs are used to speed up burst reads
(8x32) and writes (64x32) performed by the host processor to local resources, by
buffering prefetched read data and absorbing latency during consecutive writes.
target, responding to Memory Read, Memory Write, Configuration Read, and
Configuration Write commands from any initiator on the PCI bus. The slave
interface will respond only to Memory Read and Memory Write commands if the
MS_EN bit of the Command field in the PCI Configuration Register has been set.
to special cycles on the PCI bus. If a master performs a special cycle on the PCI
bus, the following occurs:
11.7 Byte Swapping of Control Structures
Two control bits in the PCI configuration space are used to configure byte
swapping, in order to align with various big and little endian host system
requirements.
Configuration register. When SLAVE_SWAP is set to a logic high, the slave
interface swaps the bytes of a slave write or read access. The default setting for
this bit is logic low.
PCI Configuration register. When MSTR_CTRL_SWAP is set to a logic high, the
control structures that the SAR writes are written with bytes swapped. The default
setting for this bit is logic low.
In general, the PCI slave interface functions as a normal memory-mapped PCI
The PCI slave logic does not implement special cycle commands, or respond
• The slave logic never asserts HDEVSEL*.
• Parity errors during the address phase of the special cycle command will
• Parity errors during the data phase are ignored.
The SLAVE_SWAP control bit is bit 29 of address offset 0x40 in the PCI
The MSTR_CTRL_SWAP control bit is bit 30 of address offset 0x40 in the
The HRST* pin made active will cause both of these bits to be logic low.
be reported to be asserting HSERR* in the normal fashion, if SE_EN and
PE_EN in the command register are both set.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
RS8234