RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 49

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
Figure 2-9. Multi-Level Model for Prioritizing Segmentation Traffic
28234-DSH-001-B
NOTE(S):
Host
(1)
(2)
(3)
(4)
(5)
The user initializes traffic parameters on a per-VCC basis.
User selects priority or round-robin service policy on transmit queues.
The segmentation coprocessor notifies the Traffic Manager when a VCC becomes active, through
reading new entries from the transmit queue.
Each conforming non-CBR VCC is assigned to a priority queue, while conforming CBR VCCs
are simply slated for transmit.
The highest priority conforming cell is formatted and put on the Tx FIFO buffer for transmit.
Buffers
Data
Parameters
Transmit Queues
(1)
Traffic
Control
Tables
VCC
(32)
schemes, as the Tx FIFO empties.
Mindspeed Technologies
The RS8234 asynchronously multiplexes traffic based on the above
(2)
Start
Templates
Schedule
Table
ABR
(3)
Segmentation
Coprocessor
xBR Traffic
Manager
Conforming
VCC ID #
16 UBR/VBR/ABR
Priority Queues
Next Tx VCC ID #
SAR
(5)
™
CBR
2.5 Advanced xBR Traffic Management
Full/Empty
(4)
UBR/VBR/ABR
VCC ID #
Tx FIFO
2.0 Architecture Overview
Buffer
To
PHY
100074_010
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