RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 356

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

15.0 Electrical and Mechanical Specifications
15.1 Timing
Table 15-10. Local Processor Memory Interface Timing
15-16
NOTE(S):
(1)
(2)
(3)
Symbol
t
t
pdaenh
t
t
pdaenl
t
t
cwdh
See
t
In the case of two cycle memory, or when inserting wait states by PWAIT*, MOE*, MWE[3:0]*, and MWR* are
extended across two or more clock cycles with the same relative timing to SYSCLK. See the functional timing diagrams in
Section 10.6
t
t
cwds
t
t
t
t
t
mcs
t
t
oeh
lav
crd
lod
loe
lav
oel
wh
las
be
wl
is valid for second and subsequent accesses during burst transfers. See functional timing diagrams.
Figure 15-13
SYSCLK to PDAEN* Low, Bus Recovery Cycle
SYSCLK to PDAEN* High, Bus Recovery Cycle
LADDR[18:2], LDATA Output Disable to PDAEN* Low,
Bus Recovery Cycle
PDAEN* High to LADDR[18:2], LDATA Output Enable,
Bus Recovery Cycle
SYSCLK to MCS*[3:0] Valid
SYSCLK to LADDR[1,0] Valid
MOE* Active from SYSCLK
MOE* Inactive from SYSCLK
MWR*, MWE[3:0] Active from SYSCLK
MWR*, MWE[3:0]* Inactive to SYSCLK
MWE[3:0]* Byte Enables Valid from SYSCLK (RAMMODE = 1)
CSR Read Data Output Valid
CSR Write Data Setup to SYSCLK
CSR Write Data Hold from SYSCLK
LADDR Setup to SYSCLK
and
Figure 15-14
(1)
(1)
for waveforms and definitions.
Parameter
(1, 3)
(1)
(1, 3)
Mindspeed Technologies
(1, 2)
(1, 3)
(1, 3)
(1)
(1)
ATM ServiceSAR Plus with xBR Traffic Management
(1)
™
Min
12
2
4
9
1
1
8
1
1
2
8
0
Max
12
20
10
16
20
6
7
1
7
28234-DSH-001-B
RS8234
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns