DS21354L Maxim Integrated Products, DS21354L Datasheet - Page 41

• Manufacturer Part Number: DS21354L
• Description: IC TXRX E1 1-CHIP 3.3V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21354L

• Function: Single-Chip Transceiver
• Interface: E1, HDLC
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: Remote and AIS Alarm Detector / Generator
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex)
SYMBOL
(MSB)
LIRST
LIRST
RCM4
RCM3
RCM2
RCM1
RCM0
RESA
TESA
POSITION
RESA
CCR5.7
CCR5.6
CCR5.5
CCR5.4
CCR5.3
CCR5.2
CCR5.1
CCR5.0
TESA
Line Interface Reset. Setting this bit from a zero to a one will initiate an
internal reset that affects the clock recovery state machine and jitter
attenuator. Normally this bit is only toggled on power-up. Must be
cleared and set again for a subsequent reset.
Receive Elastic Store Align. Setting this bit from a zero to a one may
force the receive elastic store’s write/read pointers to a minim separation
of half a frame. No action will be taken if the pointer separation is
already greater or equal to half a frame. If pointer separation is less then
half a frame, the command will be executed and data will be disrupted.
Should be toggled after RSYSCLK has been applied and is stable. Must
be cleared and set again for a subsequent align. See Section
details.
Transmit Elastic Store Align. Setting this bit from a zero to a one may
force the transmit elastic store’s write/read pointers to a minim separation
of half a frame. No action will be taken if the pointer separation is
already greater or equal to half a frame. If pointer separation is less then
half a frame, the command will be executed and data will be disrupted.
Should be toggled after TSYSCLK has been applied and is stable. Must
be cleared and set again for a subsequent align. See Section
details.
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data will appear in the RDS0M
register. See Section
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
RCM4
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NAME AND DESCRIPTION
8
for details.
RCM3
RCM2
RCM1
12
12
for
for
RCM0
(LSB)