DS21354L Maxim Integrated Products, DS21354L Datasheet - Page 66

• Manufacturer Part Number: DS21354L
• Description: IC TXRX E1 1-CHIP 3.3V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21354L

• Function: Single-Chip Transceiver
• Interface: E1, HDLC
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: Remote and AIS Alarm Detector / Generator
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

13.
The DS21354/DS21554 provide for access to both the Sa and the Si bits through three different methods.
The first method is accomplished via a hardware scheme using the RLINK/RLCLK and TLINK/TLCLK
pins (see Section 13.1). The second method involves using the internal RAF/RNAF and TAF/TNAF
registers (see Section 13.2). The third method, which is covered in Section 13.3, involves an expanded
version of the second method, and is one of the features added to the DS2154/354/554 from the original
DS2153 definition.
13.1.
On the receive side, all the received data is reported at the RLINK pin. Via RCR2, the user can control
the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create a clock that can
be used to capture the needed Sa bits. If RSYNC is programmed to output a frame boundary, it will
identify the Si bits. See Section
On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (see
Section
source any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits
through the framer without them being altered, then the device should be set up to source all five Sa bits
via the TLINK pin and the TLINK pin should be tied to the TSER pin. Si bits can be inserted through the
TSER pin via the clearing of the TCR1.3 bit. Please see the timing diagrams and the transmit data flow
diagram in Section
13.2.
On the receive side, the RAF and RNAF registers always report the data as it received in the Additional
and International bit locations. The RAF and RNAF registers are updated with the setting of the Receive
Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the
RAF and RNAF registers. It has 250ms to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit
Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the
TAF and TNAF registers. It has 250ms to update the data or else the old data will be retransmitted. Data
in the Si bit position will be overwritten if either the framer is programmed: (1) to source the Si bits from
the TSER pin, (2) in the CRC4 mode, or (3) has automatic E-bit insertion enabled. Data in the Sa bit
position is overwritten if any of the TCR2.3 to TCR2.7 bits are set to one (see Section
Please see the register descriptions for TCR1 and TCR2 and
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
Hardware Scheme
Internal Register Scheme Based On Double Frame
13.2
for details) or from the external TLINK pin. Via TCR2, the framer can be programmed to
18.2
for examples.
18.1
for detailed timing.
66 of 124
Figure 18-15
for more details.
13.1
for details).