DS21354L Maxim Integrated Products, DS21354L Datasheet - Page 44

• Manufacturer Part Number: DS21354L
• Description: IC TXRX E1 1-CHIP 3.3V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21354L

• Function: Single-Chip Transceiver
• Interface: E1, HDLC
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: Remote and AIS Alarm Detector / Generator
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex)
SSR: SYNCHRONIZER STATUS REGISTER (Address = 1E Hex)
SYMBOL
SYMBOL
CRC4SA
(MSB)
(MSB)
CRCRC
CASRC
CASSA
FASRC
FASSA
CSC5
TESF
RESE
TESE
RESF
CSC5
CSC4
CSC3
CSC2
CSC0
TESF
JALT
POSITION
POSITION
CSC4
TESE
SSR.7
SSR.6
SSR.5
SSR.4
SSR.3
SSR.2
SSR.1
SSR.0
RIR.7
RIR.6
RIR.5
RIR.4
RIR.3
RIR.2
RIR.1
RIR.0
CSC3
JALT
Transmit-Side Elastic Store Full. Set when the transmit-side elastic
store buffer fills and a frame is deleted.
Transmit-Side Elastic Store Empty. Set when the transmit-side elastic
store buffer empties and a frame is repeated.
Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches
to within 4–bits of its limit; useful for debugging jitter attenuation
operation.
Receive-Side Elastic Store Full. Set when the receive side elastic store
buffer fills and a frame is deleted.
Receive-Side Elastic Store Empty. Set when the receive side elastic store
buffer empties and a frame is repeated.
CRC Resync Criteria Met. Set when 915/1000 codewords are received
in error.
FAS Resync Criteria Met Event (FASRC). Set when three consecutive
FAS words are received in error. Note: During a CRC resync the FAS
synchronizer is brought online to verify the FAS alignment. If during this
process a FAS emulator exists, the FAS synchronizer may temporarily
align to the emulator. The FASRC will go active indicating a search for a
valid FAS has been activated.
CAS Resync Criteria Met. Set when two consecutive CAS MF
alignment words are received in error.
CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.
CRC4 Sync Counter Bit 4.
CRC4 Sync Counter Bit 3.
CRC4 Sync Counter Bit 2.
CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. The next to LSB is
not accessible.
FAS Sync Active. Set while the synchronizer is searching for alignment
at the FAS level.
CAS MF Sync Active. Set while the synchronizer is searching for the
CAS MF alignment word.
CRC4 MF Sync Active. Set while the synchronizer is searching for the
CRC4 MF alignment word.
CSC2
RESF
44 of 124
NAME AND DESCRIPTION
NAME AND DESCRIPTION
CSC0
RESE
FASSA
CRCRC
CASSA
FASRC
CRC4SA
CASRC
(LSB)
(LSB)