CY8C5466AXI-064 Cypress Semiconductor Corp, CY8C5466AXI-064 Datasheet
CY8C5466AXI-064
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CY8C5466AXI-064 Summary of contents
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... MHz, 24-bit fixed point digital filter block (DFB) to implement FIR and IIR filters Notes 1. This feature on select devices only. See Ordering Information 2. GPIOs with opamp outputs are not recommended for use with CapSense. Cypress Semiconductor Corporation Document Number: 001-66238 Rev. *A PRELIMINARY ® PSoC 5: CY8C54 Family Datasheet Programmable System-on-Chip (PSoC ® ...
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Contents 1. Architectural Overview ................................................... 3 2. Pinouts ............................................................................. 5 3. Pin Descriptions .............................................................. 9 4. CPU ................................................................................. 10 4.1 ARM Cortex-M3 CPU ............................................. 10 4.2 Cache Controller .................................................... 11 4.3 DMA and PHUB ..................................................... 11 4.4 Interrupt Controller ................................................. ...
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Architectural Overview Introducing the CY8C54 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C54 family provides configurable blocks of analog, digital, and interconnect circuitry ...
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Figure 1-1 illustrates the major components of the CY8C54 family. They are: ARM Cortex-M3 CPU subsystem Nonvolatile subsystem Programming, debug, and test subsystem Inputs and outputs Clocking Power Digital subsystem Analog subsystem PSoC’s digital subsystem provides half of its unique ...
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SIO function as a general purpose analog comparator. For devices with FS USB the USB physical interface is also provided (USBIO). When not using USB these pins may also be used for limited digital functionality and device programming. ...
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P2[6] 1 (GPIO) P2[7] 2 (SIO) P12[4] 3 (SIO) P12[5] 4 Vssb 5 Ind 6 Vboost 7 Vbat 8 Vssd 9 10 XRES (SWDIO, GPIO) P1[0] 11 (SWDCK, GPIO) P1[1] 12 (GPIO) P1[2] 13 (SWV, GPIO) P1[3] 14 (GPIO) ...
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P2[5] 1 (GPIO) P2[6] 2 (GPIO) P2[7] 3 Lines show Vddio (I2C0: SCL, SIO) P12[ I/O supply (I2C0: SDA, SIO) P12[5] 5 association (GPIO) P6[4] 6 (GPIO) P6[5] 7 (GPIO) P6[6] 8 (GPIO) P6[ Vssb ...
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Figure 2-3. Example Schematic for 100-pin TQFP Part with Power Connections Vddd C6 0.1 uF Vssd 1 P2[5] 2 P2[6] 3 P2[7] 4 P12[4], SIO 5 P12[5], SIO 6 P6[4] 7 P6[5] 8 P6[6] 9 P6[7] 10 Vssb 11 Ind ...
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Figure 2-4. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance 3. Pin Descriptions IDAC0, IDAC1, IDAC2, IDAC3 Low resistance output pin for high current DACs (IDAC). OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out High current output of uncommitted opamp Extref0, ...
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CPU 4.1 ARM Cortex-M3 CPU The CY8C54 family of devices has an ARM Cortex-M3 CPU core. The Cortex- low power 32-bit three-stage pipelined Harvard architecture CPU that delivers 1.25 DMIPS/MHz intended for deeply embedded applications ...
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Bit-band support. Atomic bit-level write and read operations. Unaligned data storage and access. Contiguous storage of data of different byte lengths. Operation at two privilege levels (privileged and user) and in two modes (thread and handler). Some instructions can only ...
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There are two PHUB masters: the CPU and the DMA controller. Both masters may initiate transactions on the bus. The DMA channels can handle peripheral communication without CPU intervention. The arbiter in the central hub determines which DMA channel is ...
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ADDRESS Phase CLK ADDR 16/32 A WRITE DATA READY Basic DMA Read Transfer without wait states 4.3.4.2 Auto Repeat DMA Auto repeat DMA is typically used when a static pattern is repetitively read from system memory and written to a ...
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Interrupt Controller The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table 4-5. Cortex-M3 Exceptions and Interrupts Exception Exception Type Number 1 Reset –3 (highest) 2 NMI –2 3 Hard fault –1 4 ...
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Table 4-6. Interrupt Vector Table Interrupt # Cortex-M3 Exception # ...
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Memory 5.1 Static RAM CY8C54 Static RAM (SRAM) is used for temporary data storage. Code can be executed at full speed from the portion of SRAM that is located in the code space. This process is slower from SRAM ...
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Memory Map The Cortex-M3 has a fixed address map, which allows peripherals to be accessed by simple memory access instructions. 5.5.1 Address Map The 4 GB address space is divided into the ranges shown in Table 5-2: Table 5-2. ...
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System Integration 6.1 Clocking System The clocking system generates, divides, and distributes clocks throughout the PSoC system. For the majority of systems, no external crystal is required. The IMO and PLL together can generate MHz ...
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MHz 4-25 MHz IMO ECO 48 MHz 24-40 MHz Doubler for USB Digital Clock Divider 16 bit Digital Clock Divider 16 bit 7 Digital Clock Divider 16 bit Digital Clock Divider 16 bit 6.1.1 Internal Oscillators 6.1.1.1 Internal Main ...
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The central timewheel can be programmed to wake the system periodically and optionally issue an interrupt. This enables flexible, periodic wakeups from low power modes or coarse timing applications. Systems that require accurate timing should use the Real Time Clock ...
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Four 16-bit clock dividers generate clocks for the analog system components that require clocking, such as ADCs and mixers. The analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. ...
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Power Modes PSoC 5 devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing ...
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Figure 6-5. Power Mode Transitions Active Manual Sleep Alternate Active 6.2.1.1 Active Mode Active mode is the primary operating mode of the device. When in active mode, the active configuration template bits control which available resources are enabled or disabled. ...
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At 2 MHz the Vboost output is limited to 2 × Vbat, and at 400 kHz Vboost is limited to 4 × Vbat. The boost converter can be operated in two different modes: active and standby. Active mode is the ...
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Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Normal Available Trip Interrupt Supply Voltage Settings Range DLVI V 2.7 V–5.5 V 2.71 V–5.45 V DDD in 250 mV increments ALVI V 2.7 V–5.5 V 2.71 V–5.45 V DDA ...
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Digital Input Path PRT[x]CTL PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Analog Capsense Global Control CAPS[x]CFG1 PRT[x]AG Analog Global Enable ...
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Digital Input Path PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Digital Input Path ...
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Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts ...
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Resistive Pull Up or Resistive Pull Down Resistive pull up or pull down, respectively, provides a series resistance in one of the data states and strong drive in the other. Pins can be used for digital input and output in ...
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Adjustable Output Level This section applies only to SIO pins. SIO port pins support the ability to provide a regulated high output level for interface to external signals that are lower in voltage than the SIO’s respective V . ...
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Special Pin Functionality Some pins on the device include additional special functionality in addition to their GPIO or SIO functionality. The specific special function pins are listed in “Pinouts” on page 5. The special features are: Digital 4 to ...
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Example Analog Components The following is a sample of the analog components available in PSoC Creator for the CY8C54 family. The exact amount of hardware resources (SC/CT blocks, routing, RAM, flash) used by a component varies with the features ...
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Document Number: 001-66238 Rev. *A PRELIMINARY ® PSoC 5: CY8C54 Family Datasheet Figure 7-2. PSoC Creator Framework Page 33 of 105 [+] Feedback ...
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Component Catalog Figure 7-3. Component Catalog The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device populated with an impressive selection of content; from simple primitives such as ...
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PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity. ...
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Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band generators ...
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ALU The ALU performs eight general-purpose functions. They are: Increment Decrement Add Subtract Logical AND Logical OR Logical XOR Pass, used to pass a value through the ALU to the shift register, mask, or another UDB register Independent of the ...
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The bits of the control register, which may be written to by the system bus, are used to drive into the routing matrix, and thus provide firmware with the opportunity to control the state of UDB processing. The status register ...
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Figure 7-12. Function Mapping Example in a Bank of UDBs 8-Bit 16-Bit Quadrature Decoder Timer PWM UDB UDB UDB UDB UDB UDB 8-Bit SPI I2C Slave 12-Bit SPI UDB UDB UDB Logic ...
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I/O Port Routing There are a total of 20 DSI routes to a typical 8-bit I/O port, 16 for data and four for drive strength control. When an I/O pin is connected to the routing, there are two primary ...
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CAN Node 1 PSoC CAN Drivers CAN Controller CAN Transceiver CAN_H CAN_L 7.5.1 CAN Features CAN2.0A/B protocol implementation - ISO 11898 compliant Standard and extended frames with bytes of data per frame Message filter ...
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Tx Buffer Status TxReq Pending TxInterrupt Request (if enabled) Rx Buffer RxMessage0 Acceptance Code 0 Status RxMessage Acceptance Code 1 RxMessage1 Available RxMessage14 Acceptance Code 14 RxInterrupt RxMessage15 Acceptance Code 15 Request (if enabled) 7.6 USB PSoC includes a dedicated ...
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Timers, Counters, and PWMs The Timer/Counter/PWM peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. As almost all embedded systems use some combination of timers, counters, and PWMs. Four of them have been ...
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Digital Filter Block Some devices in the CY8C54 family of devices have a dedicated HW accelerator block used for digital filtering. The DFB has a dedicated multiplier and accumulator that calculates a 24-bit by 24-bit multiply accumulate in one ...
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GPIO G Port The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and various analog resources and also connections ...
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ExVrefL ExVrefL1 opamp0 opamp2 swinp GPIO swfol swfol P0[4] swinn GPIO P0[5] GPIO swout * i0 abuf_vref_int P0[6] (1.024V) GPIO i2 * P0[7] cmp0_vref (1.024V) GPIO cmp_muxvn[1:0] vref_cmp1 P4[2] cmp1_vref (0.256V) bg_vda_res_en GPIO Vdda ...
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Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in CY8C38, four in the left half (abusl [0:3]) and four in the ...
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From Analog Routing From Analog Routing 8.3.2 LUT The CY8C54 family of devices contains four LUTs. The LUT is a two input, one output lookup table that is driven by any one or two of the comparators in the chip. ...
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Opamps The CY8C54 family of devices contain four general purpose opamps. Figure 8-5. Opamp GPIO Analog Global Bus Opamp Analog Global Bus VREF Analog Internal Bus Analog Switch = GPIO The opamp is uncommitted and can be configured as ...
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PGA The PGA amplifies an external or internal signal. The PGA can be configured to operate in inverting mode or noninverting mode. The PGA function may be configured for both positive and negative gains as high as 50 and ...
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Internal bias voltage generation through internal resistor ladder total common and segment outputs Up to 1/16 multiplex for a maximum of 16 backplane/common outputs front plane/segment outputs for direct drive Drives up to 736 ...
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Reference Source 8.9.1 Current DAC The current DAC (IDAC) can be configured for the ranges µ 256 µA, and 0 to 2.04 mA. The IDAC can be configured to source or sink current. 8.9.2 Voltage ...
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Down Mixer The S+H can be used as a mixer to down convert an input signal. This circuit is a high bandwidth passive sample network that can sample input signals MHz. This sampled value is then ...
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Figure 9-1. SWD Interface Connections between PSoC 5 and Programmer Host Programmer 1 The voltage levels of the Host Programmer and the PSoC 5 voltage domains involved in programming should be the same. XRES pin is powered by V programming ...
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Debug Features The CY8C54 supports the following debug features: Halt and single-step the CPU View and change CPU and peripheral registers, and RAM addresses Six program address breakpoints and two literal access breakpoints Data watchpoint events to CPU Patch ...
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Development Support The CY8C54 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started to find out more. 10.1 Documentation A suite of documentation, to ensure that you ...
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Electrical Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see ...
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Device Level Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description V Analog supply voltage and input to DDA analog core ...
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Table 11-3. AC Specifications Parameter Description F CPU frequency CPU F Bus frequency BUSCLK Svdd V ramp rate DD T Time from IO_INIT DDD DDA CCD ≥ IPOR to I/O ports set to their reset states ...
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Power Regulators Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description V Input voltage DDD V Output voltage CCD ...
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Inductive Boost Regulator. Table 11-6. Inductive Boost Regulator DC Specifications Unless otherwise specified, operating conditions are µF || 0.1 µF BOOST Parameter Description V Input voltage BAT Includes startup [18, 19] I Load current OUT ...
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Table 11-8. Recommended External Components for Boost Circuit Parameter Description L Boost inductor BOOST [22] C Filter capacitor BOOST I External Schottky F diode average forward current V R 11.4 Inputs and Outputs Specifications are valid for –40 °C ≤ ...
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Figure 11-4. GPIO Output High Voltage and Current Table 11-10. GPIO AC Specifications Parameter Description TriseF Rise time in Fast Strong Mode TfallF Fall time in Fast Strong Mode TriseS Rise time in Slow Strong Mode TfallS Fall time in ...
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SIO Table 11-11. SIO DC Specifications Parameter Description Vinmax Maximum input voltage Vinref Input voltage reference (Differential input mode) Output voltage reference (Regulated output mode) Voutref Input voltage high threshold V GPIO mode IH [24] Differential input mode Input ...
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Figure 11-8. SIO Output High Voltage and Current, Unregulated Mode Figure 11-10. SIO Output High Voltage and Current, Regulat- ed Mode Table 11-12. SIO AC Specifications Parameter Description TriseF Rise time in Fast Strong Mode [26] (90/10%) TfallF Fall time ...
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Table 11-12. SIO AC Specifications (continued) Parameter Description SIO output operating frequency Unregulated output (GPIO) mode, fast strong drive mode 3.3 V < V < 5.5 V, Unregulated DDIO output (GPIO) mode, slow strong drive mode Fsioout 2.7 V < ...
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USBIO For operation in GPIO mode, the standard range for V Table 11-13. USBIO DC Specifications Parameter Description Rusbi USB D+ pull-up resistance Rusba USB D+ pull-up resistance Vohusb Static output high Volusb Static output low Vihgpio Input voltage ...
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Table 11-14. USBIO AC Specifications Parameter Description Tdrate Full-speed data rate average bit rate Tjr1 Receiver data jitter tolerance to next transition Tjr2 Receiver data jitter tolerance to pair transition Tdj1 Driver differential jitter to next transition Tdj2 Driver differential ...
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Table 11-15. USB Driver AC Specifications Parameter Description Tr Transition rise time Tf Transition fall time TR Rise/fall time matching Vcrs Output signal crossover voltage 11.4.4 XRES Table 11-16. XRES DC Specifications Parameter Description V Input voltage high threshold IH ...
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Analog Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. 11.5.1 Opamp Table 11-18. Opamp DC Specifications Parameter Description V Input offset voltage IOFF Vos Input offset voltage TCVos Input offset ...
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Figure 11-18. Opamp Voffset vs Vcommon and Vdda, 25 °C Figure 11-20. Opamp Operating Current vs Vdda and Power Mode Table 11-19. Opamp AC Specifications Parameter Description GBW Gain-bandwidth product SR Slew rate, 20% - 80% e Input noise density ...
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Figure 11-21. Opamp Noise vs Frequency, Power Mode = High, Vdda = 5V Figure 11-23. Opamp Step Response, Falling 11.5.2 Voltage Reference Table 11-20. Voltage Reference Specifications Parameter Description V Precision reference voltage REF [28] Temperature drift Long term drift ...
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SAR ADC Table 11-21. SAR ADC DC Specifications Parameter Description Resolution Number of channels – single-ended Number of channels – differential [29] Monotonicity Ge Gain error V Input offset voltage OS I Current consumption DD Input voltage range – ...
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Comparator Table 11-24. Comparator DC Specifications Parameter Description Input offset voltage in fast mode V OS Input offset voltage in slow mode Input offset voltage in fast mode V OS Input offset voltage in slow mode V Input offset ...
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Current Digital-to-analog Converter (IDAC) See the IDAC component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-26. IDAC DC Specifications Parameter Description Resolution I Output ...
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Table 11-26. IDAC DC Specifications (continued) Parameter Description I Operating current, code = 0 DD Figure 11-24. IDAC INL vs Input Code, Range = 255 µA, Source Mode Document Number: 001-66238 Rev. *A PRELIMINARY ® PSoC 5: CY8C54 Family Datasheet ...
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Figure 11-26. IDAC DNL vs Input Code, Range = 255 µA, Source Mode Figure 11-28. IDAC INL vs Temperature, Range = 255 µA, Fast Mode Document Number: 001-66238 Rev. *A PRELIMINARY ® PSoC 5: CY8C54 Family Datasheet Figure 11-27. IDAC ...
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Figure 11-30. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode Figure 11-32. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode Document Number: 001-66238 Rev. *A PRELIMINARY ® PSoC 5: CY8C54 ...
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Table 11-27. IDAC AC Specifications Parameter Description F Update rate DAC T Settling time to 0.5 LSB SETTLE Figure 11-34. IDAC Step Response, Codes 0x40 - 0xC0, 255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V Figure 11-36. ...
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Voltage Digital to Analog Converter (VDAC) See the VDAC component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-28. VDAC DC Specifications Parameter Description Resolution ...
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Figure 11-39. VDAC INL vs Temperature Mode Figure 11-41. VDAC Full Scale Error vs Temperature Mode Figure 11-43. VDAC Operating Current vs Temperature, 1V Mode, Slow Mode Document Number: 001-66238 Rev. *A PRELIMINARY ® PSoC 5: ...
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Table 11-29. VDAC AC Specifications Parameter Description F Update rate DAC TsettleP Settling time to 0.1%, step 25% to 75% TsettleN Settling time to 0.1%, step 75% to 25% Figure 11-45. VDAC Step Response, Codes 0x40 - 0xC0 ...
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Mixer The mixer is created using a SC/CT analog block; see the Mixer component data sheet in PSoC Creator for full electrical specifications and APIs. Table 11-30. Mixer DC Specifications Parameter Description V Input offset voltage OS Quiescent current ...
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Programmable Gain Amplifier The PGA is created using a SC/CT analog block; see the PGA component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, operating conditions are: Operating temperature = 25 °C for ...
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Table 11-35. PGA AC Specifications Parameter Description BW1 –3 dB bandwidth SR1 Slew rate e Input noise density n Figure 11-54. Bandwidth vs. Temperature, at Different Gain Settings, Power Mode = High 11.5.11 Temperature Sensor Table 11-36. Temperature Sensor Specifications ...
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Digital Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. 11.6.1 Timer The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for ...
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Table 11-42. Counter AC Specifications (continued) Parameter Description Enable pulse width (external) Reset pulse width Reset pulse width (external) 11.6.3 Pulse Width Modulation The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented ...
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Controller Area Network Table 11-47. CAN DC Specifications Parameter Description I Block current consumption DD Table 11-48. CAN AC Specifications Parameter Description Bit rate 11.6.5 Digital Filter Block Table 11-49. DFB DC Specifications Parameter Description DFB operating current Table ...
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Universal Digital Blocks (UDBs) PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. See the component ...
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Memory Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. 11.7.1 Flash Table 11-53. Flash DC Specifications Parameter Description Erase and program voltage Table 11-54. Flash AC Specifications Parameter Description T Row ...
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PSoC System Resources Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. 11.8.1 Voltage Monitors Table 11-59. Voltage Monitors DC Specifications Parameter Description LVI Trip voltage LVI_A/D_SEL[3:0] = 0011b LVI_A/D_SEL[3:0] = 0100b ...
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SWD Interface Table 11-65. SWD Interface AC Specifications Parameter Description f_SWDCK SWDCLK frequency T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max T_SWDI_hold SWDIO input hold after SWDCK high T_SWDO_valid SWDCK high to SWDIO output T_SWDO_hold SWDIO ...
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Clocking Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A where noted. Unless otherwise specified, all charts and graphs show typical values. 11.9.1 32 kHz External Crystal Table 11-67. 32 kHz External Crystal DC ...
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Figure 11-57. IMO Current vs. Frequency Table 11-70. IMO AC Specifications Parameter Description IMO frequency stability (with factory trim) 62.6 MHz 48 MHz F 24 MHz IMO 12 MHz 6 MHz 3 MHz [43] Startup time [43] Jitter (peak to ...
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Figure 11-58. IMO Frequency Variation vs. Temperature 11.9.3 Internal Low Speed Oscillator Table 11-71. ILO DC Specifications Parameter Description Operating current I CC Leakage current Table 11-72. ILO AC Specifications Parameter Description Startup time, all frequencies ILO frequencies (trimmed) 100 ...
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External Crystal Oscillator Table 11-73. ECO AC Specifications Parameter Description F Crystal frequency range 11.9.5 External Clock Reference Table 11-74. External Clock Reference AC Specifications Parameter Description External frequency range Input duty cycle range Input edge rate 11.9.6 Phase-Locked ...
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... CY8C5467AXI-011 67 128 32 2 ✔ CY8C5467LTI-007 67 128 32 2 ✔ CY8C5466AXI-064 ✔ CY8C5466LTI-063 Notes 47. Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See can be used. 48. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs ...
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Part Numbering Conventions PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric ( … …, Z) unless stated otherwise. CY8Cabcdefg-xxx a: Architecture 3: PSoC 3 5: PSoC ...
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Packaging Table 13-1. Package Characteristics Parameter Description T Operating ambient temperature A T Operating junction temperature J Package θJA (68-pin QFN) Tja Package θJA (100-pin TQFP) Tja Package θJC (68-pin QFN) Tjc Package θJC (100-pin TQFP) Tjc Table 13-2. ...
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Figure 13-2. 100-pin TQFP ( 1.4 mm) Package Outline Document Number: 001-66238 Rev. *A PRELIMINARY ® PSoC 5: CY8C54 Family Datasheet 51-85048 *E Page 100 of 105 [+] Feedback ...
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Acronyms Table 14-1. Acronyms Used in this Document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus archi- tecture) high-performance bus, an ARM data transfer bus ALU arithmetic logic unit AMUXBUS ...
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Table 14-1. Acronyms Used in this Document (continued) Acronym Description PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration data sheet POR power-on reset PRS pseudo random sequence PS port read ...
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Document Conventions 16.1 Units of Measure Table 16-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz kΩ kilohms ksps kilosamples ...
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Revision History ® Description Title: PSoC 5: CY8C54 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-66238 Submission Rev. ECN No. Date ** 3198501 03/17/2011 *A 3279676 06/10/2011 Document Number: 001-66238 Rev. *A PRELIMINARY ® PSoC 5: CY8C54 Family Datasheet ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...