CY8C5466AXI-064 Cypress Semiconductor Corp, CY8C5466AXI-064 Datasheet - Page 45

• Manufacturer Part Number: CY8C5466AXI-064
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5466AXI-064

• Lead Free Status / Rohs Status: Compliant

The PSoC Creator software program provides a user friendly
interface to configure the analog connections between the GPIO
and various analog resources and also connections from one
analog resource to another. PSoC Creator also provides
component libraries that allow you to configure the various
analog blocks to perform application specific functions (PGA,
transimpedance amplifier, voltage DAC, current DAC, and so
on). The tool also generates API interface libraries that allow you
to write firmware that allows the communication between the
analog peripheral and CPU/Memory.
8.1 Analog Routing
The CY8C38 family of devices has a flexible analog routing
architecture that provides the capability to connect GPIOs and
different analog blocks, and also route signals between different
analog blocks. One of the strong points of this flexible routing
architecture is that it allows dynamic routing of input and output
connections to the different analog blocks. All analog routing
switches are open when the device is in sleep or hibernate mode.
For information on how to make pin selections for optimal analog
routing, refer to the application note,
PSoC
Document Number: 001-66238 Rev. *A
®
5 - Pin Selection for Analog Designs.
GPIO
Port
A
N
A
L
O
G
R
O
U
T
N
G
I
AN58304 - PSoC
Figure 8-1. Analog Subsystem Block Diagram
PRELIMINARY
DAC
DAC
SAR
ADC
®
3 and
Array
DSI
CMP
SC/CT Block
SC/CT Block
CapSense Subsystem
CMP
8.1.1 Features
8.1.2 Functional Description
Analog globals (AGs) and analog mux buses (AMUXBUS)
provide analog connectivity between GPIOs and the various
analog blocks. There are 16 AGs in the CY8C38 family. The
analog routing architecture is divided into four quadrants as
shown in
(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is
connected to the corresponding AG through an analog switch.
The analog mux bus is a shared routing resource that connects
to every GPIO through an analog switch. There are two
AMUXBUS routes in CY8C38, one in the left half (AMUXBUSL)
and one in the right half (AMUXBUSR), as shown in
Comparators
Distribution
Flexible, configurable analog routing architecture
16 Analog globals (AG) and two analog mux buses
(AMUXBUS) to connect GPIOs and the analog blocks
Each GPIO is connected to one analog global and one analog
mux bus
8 Analog local buses (abus) to route signals between the
different analog blocks
Multiplexers and switches for input and output selection of the
analog blocks
Interface
Analog
PSoC
Clock
CMP
SC/CT Block
SC/CT Block
Figure
Registers
Config &
Reference
Precision
Status
®
CMP
Decimator
5: CY8C54 Family Datasheet
8-2. Each quadrant has four analog globals
PHUB
SAR
ADC
DAC
DAC
CPU
A
N
A
L
O
G
R
O
U
T
N
G
I
GPIO
Page 45 of 105
Port
Figure
8-2.
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