CY8C5466AXI-064 Cypress Semiconductor Corp, CY8C5466AXI-064 Datasheet - Page 51

• Manufacturer Part Number: CY8C5466AXI-064
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5466AXI-064

• Lead Free Status / Rohs Status: Compliant

Figure 8-9. LCD System
8.6.1 LCD Segment Pin Driver
Each GPIO pin contains an LCD driver circuit. The LCD driver
buffers the appropriate output of the LCD DAC to directly drive
the glass of the LCD. A register setting determines whether the
pin is a common or segment. The pin’s LCD driver then selects
one of the six bias voltages to drive the I/O pin, as appropriate
for the display data.
8.6.2 Display Data Flow
The LCD segment driver system reads display data and
generates the proper output voltages to the LCD glass to
produce the desired image. Display data resides in a memory
buffer in the system SRAM. Each time you need to change the
common and segment driver voltages, the next set of pixel data
moves from the memory buffer into the Port Data Registers via
DMA.
Document Number: 001-66238 Rev. *A
Internal bias voltage generation through internal resistor ladder
Up to 62 total common and segment outputs
Up to 1/16 multiplex for a maximum of 16 backplane/common
outputs
Up to 62 front plane/segment outputs for direct drive
Drives up to 736 total segments (16 backplane x 46 front plane)
Up to 64 levels of software controlled contrast
Ability to move display data from memory buffer to LCD driver
through DMA (without CPU intervention)
Adjustable LCD refresh rate from 10 Hz to 150 Hz
Ability to invert LCD display for negative image
Three LCD driver drive modes, allowing power optimization
LCD driver configurable to be active when PSoC is in limited
active mode
Global
Clock
DMA
UDB
Display
RAM
PHUB
LCD Driver
Block
DAC
LCD
PRELIMINARY
PIN
8.6.3 UDB and LCD Segment Control
A UDB is configured to generate the global LCD control signals
and clocking. This set of signals is routed to each LCD pin driver
through a set of dedicated LCD global routing channels. In
addition to generating the global LCD control signals, the UDB
also produces a DMA request to initiate the transfer of the next
frame of LCD data.
8.6.4 LCD DAC
The LCD DAC generates the contrast control and bias voltage
for the LCD system. The LCD DAC produces up to five LCD drive
voltages plus ground, based on the selected bias ratio. The bias
voltages are driven out to GPIO pins on a dedicated LCD bias
bus, as required.
8.7 CapSense
The CapSense system provides a versatile and efficient means
for measuring capacitance in applications such as touch sense
buttons, sliders, proximity detection, etc. The CapSense system
uses a configuration of system resources, including a few
hardware functions primarily targeted for CapSense. Specific
resource usage is detailed in the CapSense component in PSoC
Creator.
A capacitive sensing method using a delta-sigma modulator
(CSD) is used. It provides capacitance sensing using a switched
capacitor technique with a delta-sigma modulator to convert the
sensing current to a digital code.
8.8 Temp Sensor
Die temperature is used to establish programming parameters
for writing flash. Die temperature is measured using a dedicated
sensor based on a forward biased transistor. The temperature
sensor has its own auxiliary ADC.
8.9 DAC
The CY8C54 parts contain four Digital to Analog Convertors
(DACs). Each DAC is 8-bit and can be configured for either
voltage or current output. The DACs support CapSense, power
supply regulation, and waveform generation. Each DAC has the
following features.
Adjustable voltage or current output in 255 steps
Programmable step size (range selection)
Eight bits of calibration to correct ± 25% of gain error
Source and sink option for current output
8 Msps conversion rate for current output
1 Msps conversion rate for voltage output
Monotonic in nature
Data and strobe inputs can be provided by the CPU or DMA,
or routed directly from the DSI
Dedicated low-resistance output pin for high-current mode
PSoC
®
5: CY8C54 Family Datasheet
Page 51 of 105
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