CY8C5466AXI-064 Cypress Semiconductor Corp, CY8C5466AXI-064 Datasheet - Page 22

• Manufacturer Part Number: CY8C5466AXI-064
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5466AXI-064

• Lead Free Status / Rohs Status: Compliant

6.2.1 Power Modes
PSoC 5 devices have four different power modes, as shown in
Table 6-2
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low power and portable devices.
PSoC 5 power modes, in order of decreasing power
consumption are:
Table 6-2. Power Modes
Table 6-3. Power Modes Wakeup Time and Power Consumption
Document Number: 001-66238 Rev. *A
Power Modes
Active
Alternate
Active
Sleep
Hibernate
Note
Active
Alternate
Active
Sleep
Hibernate
7. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See
Active
Alternate Active
Sleep
Hibernate
Modes
Sleep
and
20 µs typ
Wakeup
<100 µs
Table
Time
Primary mode of operation,
all peripherals available
(programmable)
Similar to Active mode, and is
typically configured to have
fewer peripherals active to
reduce power. One possible
configuration is to use the
UDBs for processing, with the
CPU turned off
All subsystems automatically
disabled
All subsystems automatically
disabled
Lowest power consuming
mode with all peripherals and
internal regulators disabled,
except hibernate regulator is
enabled
Configuration and memory
contents retained
–
–
6-3. The power modes allow a design to
Description
Current
5 mA
(Typ)
3 µA
1 µA
–
[7]
Execution
defined
Code
User
Yes
No
No
PRELIMINARY
Wakeup, reset,
manual register
entry
Manual register
entry
Manual register
entry
Manual register
entry
Entry Condition Wakeup Source
Resources
Digital
None
None
All
All
Table 11-2 on page
Resources
Any interrupt
Any interrupt
PICU, RTC,
CTW, LVD
PICU
Analog
None
None
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and Real Time Clock
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only
from I/O pins.
between power modes. Sleep and hibernate modes should not
be entered until all V
All
All
58.
PSoC
Clock Sources
ILO/kHzECO
Available
®
Figure 6-5
Any (programmable) All regulators available.
Any (programmable) All regulators available.
ILO/kHzECO
None
5: CY8C54 Family Datasheet
All
All
Active Clocks
DDIO
illustrates the allowable transitions
supplies are at valid voltage levels.
Wakeup Sources
PICU, RTC, CTW,
PICU
LVD
–
–
Digital and analog
regulators can be disabled
if external regulation used.
Digital and analog
regulators can be disabled
if external regulation used.
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Only hibernate regulator
active.
Regulator
Page 22 of 105
XRES, LVD,
Sources
Reset
XRES
WDR
All
All
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