CY8C5466AXI-064 Cypress Semiconductor Corp, CY8C5466AXI-064 Datasheet - Page 54

• Manufacturer Part Number: CY8C5466AXI-064
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5466AXI-064

• Lead Free Status / Rohs Status: Compliant

Document Number: 001-66238 Rev. *A
V
2
3
4
1
level as Host V
level as host Programmer. The Port 1 SWD pins are powered by V
voltage level as host V
the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require
external interface circuitry to toggle power which will depend on the programming setup. The power
supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or
equal to all other supplies.
using external pull-down resistor (around 100 K resistor). This is required for P15[7] SWDCK signal to be seen by
PSoC 5's internal logic.
Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5.
For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have
When USB SWD pins are used for Programming, the P1[1] SWDCK pin must be externally connected to Ground
The voltage levels of the Host Programmer and the PSoC 5 voltage domains involved in programming should be
the same. XRES pin is powered by V
programming using the USB SWD pins with XRES pin, the V
DDIO3
) need not be at the same voltage level as host Programmer.
Host Programmer
Figure 9-1. SWD Interface Connections between PSoC 5 and Programmer
DD
. Rest of PSoC 5 voltage domains (V
DD
for Port 1 SWD programming. Rest of PSoC 5 voltage domains ( V
SWDCK
SWDIO
XRES
V
GND
PRELIMINARY
DD
DDIO1
. The USB SWD pins are powered by V
GND
V
DD
DDA
, V
DDIO0
DDD
, V
PSoC
, V
DDIO2
DDIO1
DDIO1
, V
. So V
DDIO3
of PSoC 5 should be at the same voltage
V
V
SWDIO (P1[0] or P15[6])
SWDCK (P1[1] or P15[7])
®
XRES
SSD
DDD
) need not be at the same voltage
, V
, V
5: CY8C54 Family Datasheet
DDIO1
SSA
DDA
, V
DDD
of PSoC 5 should be at same
DDIO0
. So for
, V
PSoC 5
DDIO1
DDD
, V
DDIO2
, V
4
DDA
, V
DDIO3
, V
DDIO0
1, 2, 3
, V
DDIO2
Page 54 of 105
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