CY8C5466AXI-064 Cypress Semiconductor Corp, CY8C5466AXI-064 Datasheet - Page 24

• Manufacturer Part Number: CY8C5466AXI-064
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5466AXI-064

• Lead Free Status / Rohs Status: Compliant

At 2 MHz the Vboost output is limited to 2 × Vbat, and at 400 kHz
Vboost is limited to 4 × Vbat.
The boost converter can be operated in two different modes:
active and standby. Active mode is the normal mode of operation
where the boost regulator actively generates a regulated output
voltage. In standby mode, most boost functions are disabled,
thus reducing power consumption of the boost circuit. The
converter can be configured to provide low power, low current
regulation in the standby mode. The external 32 kHz crystal can
be used to generate inductor boost pulses on the rising and
falling edge of the clock when the output voltage is less than the
programmed value. This is called automatic thump mode (ATM).
The boost typically draws 200 µA in active mode and 12 µA in
standby mode. The boost operating modes must be used in
conjunction with chip power modes to minimize the total chip
power consumption.
available in different chip power modes.
Table 6-4. Chip and Boost Power Modes Compatibility
If the boost converter is not used in a given application, tie the
V
unconnected.
6.3 Reset
CY8C54 has multiple internal and external reset sources
available. The reset sources are:
Document Number: 001-66238 Rev. *A
Chip –Active mode
Chip –Sleep mode
Chip–Hibernate mode Boost can only be operated in active
BAT
Chip Power Modes
Power source monitoring - The analog and digital power
voltages, V
several different modes during power up, active mode, and
sleep mode (buzzing). If any of the voltages goes outside
predetermined ranges then a reset is generated. The monitors
are programmable to generate an interrupt to the processor
under certain conditions before reaching the reset thresholds.
External - The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull up to Vddio1. V
have voltage applied before the part comes out of reset.
Watchdog timer - A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset. The watchdog timer should not be used
during sleep and hibernate modes.
Software - The device can be reset under program control.
, V
SSB
, and V
DDA
, V
BOOST
DDD
Table 6-4
, V
Boost can be operated in either active
or standby mode.
Boost can be operated in either active
or standby mode. However, it is recom-
mended to operate boost in standby
mode for low power consumption
mode. However, it is recommended not
to use boost in chip hibernate mode
due to high current consumption in
boost active mode
pins to ground and leave the Ind pin
CCA
DDD
, and V
lists the boost power modes
Boost Power Modes
, V
DDA
CCD
, and Vddio1 must all
are monitored in
PRELIMINARY
Figure 6-7. Resets
The term system reset indicates that the processor as well as
analog and digital peripherals and registers are reset. A reset
status register holds the source of the most recent reset or power
voltage monitoring interrupt. The program may examine this
register to detect and report exception conditions. This register
is cleared after a power on reset.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors
Reset
Pin
IPOR - Initial Power-on Reset
At initial power on, IPOR monitors the power voltages V
and V
corresponding internal regulators. The trip level is not precise.
It is set to approximately 1 volt, which is below the lowest
specified operating voltage but high enough for the internal
circuits to be reset and to hold their reset state. The monitor
generates a reset pulse that is at least 100 ns wide. It may be
much wider if one or more of the voltages ramps up slowly.
To save power the IPOR circuit is disabled when the internal
digital supply is stable. When the voltage is high enough, the
IMO starts.
ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog
High Voltage Interrupt
Interrupt circuits are available to detect when V
go outside a voltage range. For AHVI, V
fixed trip level. For ALVI and DLVI, V
compared to trip levels that are programmable, as listed in
Table
a device reset instead of an interrupt.
PSoC
DDA
6-5. ALVI and DLVI can also be configured to generate
Vddd Vdda
Watchdog
, both directly at the pins and at the outputs of the
Monitors
Software
External
Register
Voltage
®
Power
Reset
Timer
Reset
Level
5: CY8C54 Family Datasheet
Controller
Reset
DDA
DDA
and V
is compared to a
Page 24 of 105
System
DDA
DDD
Processor
Reset
Interrupt
and V
are
DDD
DDD
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