CY8C5466AXI-064 Cypress Semiconductor Corp, CY8C5466AXI-064 Datasheet - Page 21

• Manufacturer Part Number: CY8C5466AXI-064
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5466AXI-064

• Lead Free Status / Rohs Status: Compliant

Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50% duty
cycle clocks, system clock resynchronization logic, and deglitch
logic. The outputs from each digital clock tree can be routed into
the digital system interconnect and then brought back into the
clock system as an input, allowing clock chaining of up to 32 bits.
6.1.4 USB Clock Domain
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
Note The two V
shown in
Document Number: 001-66238 Rev. *A
Four 16-bit clock dividers generate clocks for the analog system
components that require clocking, such as ADCs and mixers.
The analog clock dividers include skew control to ensure that
critical analog events do not occur simultaneously with digital
switching events. This is done to reduce analog system noise.
Figure
CCD
2-4.
pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
Vddio1
Vddio2
Vssb
0.1 µF
0.1 µF
I/O Supply
I/O Supply
Domain
Digital
PRELIMINARY
Figure 6-4. PSoC Power System
1 µF
Regulators
Digital
0.1µF
Vddd
Vddd
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
6.2 Power System
The power system consists of separate analog, digital, and I/O
supply pins, labeled V
also includes two internal 1.8 V regulators that provide the digital
(V
The output pins of the regulators (V
pins must have capacitors connected as shown in
The two V
trace as possible, and connected to a 1 µF ±10% X5R capacitor.
The power system also contains a sleep regulator and a
hibernate regulator.
CCD
PSoC
) and analog (V
0.1 µF
I/O Supply
Regulator
Regulator
CCD
Hibernate
Regulator
Analog
Sleep
Domain
Analog
®
I/O Supply
pins must be shorted together, with as short a
5: CY8C54 Family Datasheet
0.1 µF
Vddio0
CCA
DDA
Vdda
Vcca
Vssa
Vddio3
) supplies for the internal core logic.
, V
DDD
Vddio0
, and Vddiox, respectively. It
CCD
1 µF
0.1 µF
Vdda
and V
0.1 µF
.
CCA
Page 21 of 105
) and the V
Figure
6-4.
DDIO
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