CY8C5466AXI-064 Cypress Semiconductor Corp, CY8C5466AXI-064 Datasheet - Page 52

• Manufacturer Part Number: CY8C5466AXI-064
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5466AXI-064

• Lead Free Status / Rohs Status: Compliant

8.9.1 Current DAC
The current DAC (IDAC) can be configured for the ranges 0 to
32 µA, 0 to 256 µA, and 0 to 2.04 mA. The IDAC can be
configured to source or sink current.
8.9.2 Voltage DAC
For the voltage DAC (VDAC), the current DAC output is routed
through resistors. The two ranges available for the VDAC are 0
to 1.024 V and 0 to 4.096 V. In voltage mode any load connected
to the output of a DAC should be purely capacitive (the output of
the VDAC is not buffered).
8.10 Up/Down Mixer
In continuous time mode, the SC/CT block components are used
to build an up or down mixer. Any mixing application contains an
input signal frequency and a local oscillator frequency. The
polarity of the clock, Fclk, switches the amplifier between
inverting or noninverting gain. The output is the product of the
input and the switching function from the local oscillator, with
frequency components at the local oscillator plus and minus the
signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level
frequency components at odd integer multiples of the local
oscillator frequency. The local oscillator frequency is provided by
the selected clock source for the mixer.
Continuous time up and down mixing works for applications with
input signals and local oscillator frequencies up to 1 MHz.
Document Number: 001-66238 Rev. *A
Reference
Source
PRELIMINARY
Figure 8-10. DAC Block Diagram
Scaler
Figure 8-11. Mixer Configuration
8.11 Sample and Hold
The main application for a sample and hold, is to hold a value
stable while an ADC is performing a conversion. Some
applications require multiple signals to be sampled
simultaneously, such as for power calculations (V and I).
Figure 8-12. Sample and Hold Topology
( Φ 1 and Φ 2 are opposite phases of a clock)
sc_clk
V
V
Vin
Vref
n
i
ref
PSoC
I
I
1x , 8x , 64x
1x , 8x , 64x
source
sink
R
mix
Range
Range
0 20 k or 40 k
®
Φ
Φ
Φ
Φ
3R
R
5: CY8C54 Family Datasheet
2
2
1
1
0
1
C
C
1
3
Vout
C2 = 1.7 pF
C1 = 850 fF
R
Φ
Φ
Φ
Φ
mix
1
sc_clk
2
2
1
0 20 k or 40 k
Iout
C
C
2
4
Φ
Φ
Φ
Φ
Page 52 of 105
1
2
1
2
V
V
ref
ref
Vout
V
out
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