CY8C5466AXI-064 Cypress Semiconductor Corp, CY8C5466AXI-064 Datasheet - Page 58

• Manufacturer Part Number: CY8C5466AXI-064
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5466AXI-064

• Lead Free Status / Rohs Status: Compliant

11.2 Device Level Specifications
Specifications are valid for –40 °C ≤ T
where noted.
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Notes
Document Number: 001-66238 Rev. *A
V
V
V
V
V
V
V
I
Parameter
13. The power supplies can be brought up in any sequence however once stable V
14. The V
15. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective data sheets, available in
16. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.
DD
DDA
DDA
DDD
DDD
DDIO
CCA
CCD
PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device data sheet and component data sheets
[15]
[14]
DDIO
supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ V
Analog supply voltage and input to
analog core regulator
Analog supply voltage, analog
regulator bypassed
Digital supply voltage relative to
V
Digital supply voltage, digital
regulator bypassed
I/O supply voltage relative to V
Direct analog core voltage input
(Analog regulator bypass)
Direct digital core voltage input
(Digital regulator bypass)
Active Mode, V
Execute from Flash cache, see
Cache Controller
Flash Program Memory
Sleep Mode
CPU = OFF
RTC = ON (= ECO32K ON, in low
power mode)
Sleep timer = ON (= ILO ON at
1 kHz)
WDT = OFF
POR = ON
Boost = OFF
SIO pins in single ended input,
unregulated output mode
Hibernate Mode
Hibernate mode current
All regulators and oscillators off.
SRAM retention
GPIO interrupts are active
Boost = OFF
SIO pins in single ended input,
unregulated output mode
SSD
Description
[16]
DD
on page 11 and
= 2.7 V – 5.5 V
A
on page 16
≤ 85 °C and T
SSIO
PRELIMINARY
Analog core regulator enabled
Analog core regulator disabled
Digital core regulator enabled
Digital core regulator disabled
Analog core regulator disabled
Digital core regulator disabled
CPU at 6 MHz
V
V
V
V
DD
DD
DD
DD
J
≤ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except
= V
= V
= V
= V
DDIO
DDIO
DDIO
DDIO
= 4.5 – 5.5 V T= –40 °C
= 2.7 – 3.6 V T= –40 °C
= 4.5 – 5.5 V T= –40 °C
= 2.7 – 3.6 V T= –40 °C
DDA
Conditions
must be greater than or equal to all other supplies.
PSoC
T = –40 °C
T = 25 °C
T = 85 °C
T= 25 °C
T= 85 °C
T= 25 °C
T= 85 °C
T= 25 °C
T= 85 °C
T= 25 °C
T= 85 °C
®
5: CY8C54 Family Datasheet
1.71
1.71
1.71
1.71
Min
2.7
2.7
2.7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1000
Typ
1.8
1.8
1.8
1.8
–
–
–
–
5
–
–
–
–
–
3
–
–
–
–
–
–
V
V
DDA
DDA
1.89
1.89
1.89
Max
1.89
Page 58 of 105
5.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
[13]
[13]
DDIO
Units
≤ V
mA
mA
mA
µA
µA
µA
µA
µA
µA
nA
nA
nA
nA
nA
nA
V
V
V
V
V
V
V
DDA
.
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