ATmega32C1 Automotive Atmel Corporation, ATmega32C1 Automotive Datasheet - Page 113

• Manufacturer Part Number: ATmega32C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega32C1 Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

13.4
7647G–AVR–09/11
Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter
unit.
Figure 13-2. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH)
containing the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower
eight bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU
does an access to the TCNTnH I/O location, the CPU accesses the high byte temporary regis-
ter (TEMP). The temporary register is updated with the TCNTnH value when the TCNTnL is
read, and TCNTnH is updated with the temporary register value when TCNTnL is written. This
allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the
8-bit data bus. It is important to notice that there are special cases of writing to the TCNTn
Register when the counter is counting that will give unpredictable results. The special cases
are described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decre-
mented at each timer clock (clk
clock source, selected by the Clock Select bits (CSn2:0). When no clock source is selected
(CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be accessed by the CPU,
independent of whether clk
counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OCnx. For more details about advanced count-
ing sequences and waveform generation, see
Count
Direction
Clear
clk
TOP
BOTTOM
RTG
T
Figure 13-2
n
TCNTnH (8-bit)
TEMP (8-bit)
TCNTn (16-bit Counter)
Increment or decrement TCNTn by 1.
Select between increment and decrement.
Clear TCNTn (set all bits to zero).
Timer/Counter clock.
Signalize that TCNTn has reached maximum value.
Signalize that TCNTn has reached minimum value (zero).
An external event (ICP1A or ICP1B) asks for a TOP like action.
DATA BUS
shows a block diagram of the counter and its surroundings.
TCNTnL (8-bit)
(8-bit)
T
n
is present or not. A CPU write overrides (has priority over) all
T
n
). The clk
Atmel ATmega16/32/64/M1/C1
Direction
Count
Clear
RTG
Control Logic
T
n
“16-bit Timer/Counter1 with PWM” on page
can be generated from an external or internal
TOP BOTTOM
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
Tn
107.
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