ATmega32C1 Automotive Atmel Corporation, ATmega32C1 Automotive Datasheet - Page 166

• Manufacturer Part Number: ATmega32C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega32C1 Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

15.2.6
15.3
166
Data Modes
Atmel ATmega16/32/64/M1/C1
SPI Data Register – SPDR
• Bits 7:0 - SPD7:0: SPI Data
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the reg-
ister causes the Shift Register Receive buffer to be read.
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
ure 15-3
SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by sum-
marizing
Table 15-5.
Figure 15-3. SPI Transfer Format with CPHA = 0
Bit
Read/Write
Initial Value
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
Table 15-2
and
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
Figure
MSB first (DORD = 0)
LSB first (DORD = 1)
CPOL Functionality
SPD7
R/W
X
7
and
15-4. Data bits are shifted out and latched in on opposite edges of the
SPD6
R/W
Table
X
6
MSB
LSB
15-3, as done below:
Sample (Falling)
SPD5
Sample (Rising)
R/W
Leading Edge
Setup (Falling)
Setup (Rising)
X
5
Bit 6
Bit 1
SPD4
R/W
X
4
Bit 5
Bit 2
SPD3
R/W
Bit 4
Bit 3
X
3
Sample (Falling)
Sample (Rising)
Setup (Falling)
Setup (Rising)
Trailing eDge
Bit 3
Bit 4
SPD2
R/W
X
2
Bit 2
Bit 5
SPD1
R/W
1
X
Bit 1
Bit 6
SPD0
R/W
X
0
7647G–AVR–09/11
LSB
MSB
SPI Mode
Undefined
0
1
2
3
SPDR
Fig-