ATmega32C1 Automotive Atmel Corporation, ATmega32C1 Automotive Datasheet - Page 115

• Manufacturer Part Number: ATmega32C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega32C1 Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

13.5.1
13.5.2
13.5.3
7647G–AVR–09/11
Input Capture Trigger Source
Noise Canceler
Using the Input Capture Unit
The ICRn Register can only be written when using a Waveform Generation mode that utilizes
the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera-
tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn
Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O loca-
tion before the low byte is written to ICRnL.
For more information on how to access the 16-bit registers refer to
ters” on page
The ICF1 output can be used to retrigger the timer counter. It has the same effect than the
TOP signal.
The trigger sources for the Input Capture unit arethe Input Capture pin (ICP1A & ICP1B).
Be aware that changing trigger source can trigger a capture. The Input Capture Flag must
therefore be cleared after the change.
The Input Capture pin (ICPn) IS sampled using the same technique as for the Tn pin
11-1 on page
enabled, additional logic is inserted before the edge detector, which increases the delay by
four system clock cycles. Note that the input of the noise canceler and edge detector is always
enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICRn to
define TOP.
An Input Capture can be triggered by software by controlling the port of the ICPn pin.
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing
the output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in
Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces
additional four system clock cycles of delay from a change applied to the input, to the update
of the ICRn Register. The noise canceler uses the system clock and is therefore not affected
by the prescaler.
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICRn Register before the next event occurs, the ICRn will
be overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in the inter-
rupt handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during operation, is not recommended.
109.
87). The edge detector is also identical. However, when the noise canceler is
Atmel ATmega16/32/64/M1/C1
“Accessing 16-bit Regis-
(Figure
115