ATmega32C1 Automotive Atmel Corporation, ATmega32C1 Automotive Datasheet - Page 288

• Manufacturer Part Number: ATmega32C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega32C1 Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

24.7.6
24.7.7
24.7.8
24.7.9
288
Atmel ATmega16/32/64/M1/C1
Prevent Reading the RWW Section During Self-Programming
Setting the Boot Loader Lock Bits by SPM
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
During Self-Programming (either Page Erase or Page Write), the RWW section is always
blocked for reading. The user software itself must prevent that this section is addressed during
the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW
section is busy. During Self-Programming the Interrupt Vector table should be moved to the
BLS as described in XXXXXXX, or the interrupts must be disabled. Before addressing the
RWW section after the programming is completed, the user software must clear the RWWSB
by writing the RWWSRE. See
290
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR
and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock
bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any
software update by the MCU.
See
Flash access.
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended
to load the Z-pointer with 0x0001 (same as used for reading the lO
bility it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits.
When programming the Lock bits the entire Flash can be read during the operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading
the Fuses and Lock bits from software will also be prevented during the EEPROM write opera-
tion. It is recommended that the user checks the status bit (EEWE) in the EECR Register and
verifies that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in
SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET
and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruc-
tion is executed within three CPU cycles or no SPM instruction is executed within four CPU
cycles. When BLBSET and SPMEN are cleared, LPM will work as described in the Instruction
set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SPMEN bits in SPMCSR.
Bit
R0
Bit
Rd
for an example.
Table 24-2
and
7
1
7
–
Table 24-3
6
1
6
–
“Simple Assembly Code Example for a Boot Loader” on page
for how the different settings of the Boot Loader bits affect the
BLB12
BLB12
5
5
BLB11
BLB11
4
4
BLB02
BLB02
3
3
BLB01
BLB01
2
2
ck
bits). For future compati-
LB2
1
1
1
LB1
7647G–AVR–09/11
0
0
1