ATmega32C1 Automotive Atmel Corporation, ATmega32C1 Automotive Datasheet - Page 21

• Manufacturer Part Number: ATmega32C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega32C1 Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

4.2
4.2.1
7647G–AVR–09/11
SRAM Data Memory
SRAM Data Access Times
Figure 4-2
The ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can
be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions.
For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
The lower 2304 data memory locations address both the Register File, the I/O memory,
Extended I/O memory, and the internal data SRAM. The first 32 locations address the Regis-
ter File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O
memory, and the next 1024/2048/4096 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address
given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
the 1024/2048/4096 bytes of internal data SRAM in the ATmega16/32/64/M1/C1 are all acces-
sible through all these addressing modes. The Register File is described in
Register File” on page
Figure 4-2.
This section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clk
on page
22.
shows how the ATmega16/32/64/M1/C1 SRAM Memory is organized.
Data Memory Map for 1024/2048/4096 Internal SRAM
15.
64 I/O Registers
160 Ext I/O Reg.
Internal SRAM
Data Memory
32 Registers
(1024x8)
(2048x8)
(4096x8)
Atmel ATmega16/32/64/M1/C1
0x0000 - 0x001F
0x04FF/0x08FF/0x10FF
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
CPU
cycles as described in
“General Purpose
Figure 4-3
21