SAM7S32 Atmel Corporation, SAM7S32 Datasheet - Page 52

• Manufacturer Part Number: SAM7S32
• Manufacturer: Atmel Corporation

Specifications of SAM7S32

• Flash (kbytes): 32 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 21
• Ext Interrupts: 21
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

12.5.4
12.5.4.1
52
SAM7S Series
IEEE 1149.1 JTAG Boundary Scan
JTAG Boundary-scan Register
Table 12-2.
For further details on the Debug Unit, see the Debug Unit section.
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging
technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST
and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds
with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1
JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per-
formed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up testing.
The Boundary-scan Register (BSR) contains 96 bits that correspond to active pins and associ-
ated control signals.
Each SAM7Sxx input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit
contains data that can be forced on the pad. The INPUT bit facilitates the observability of data
applied to the pad. The CONTROL bit selects the direction of the pad.
Table 12-3.
AT91SAM7S64 Rev C
AT91SAM7S128 Rev A
AT91SAM7S128 Rev B
AT91SAM7S128 Rev C
AT91SAM7S256 Rev A
AT91SAM7S256 Rev B
AT91SAM7S256 Rev C
AT91SAM7S512 Rev A
AT91SAM7S512 Rev B
Bit Number
96
95
94
93
92
91
SAM7S Series Debug Unit Chip ID (Continued)
SAM7Sxx JTAG Boundary Scan Register
PA17/PGMD5/AD0
PA18/PGMD6/AD1
Pin Name
Pin Type
IN/OUT
IN/OUT
0x270B0A40
0x270B0A4F
0x270C0740
0x270A0741
0x270A0742
0x270D0940
0x270B0941
0x270B0942
0x27090544
Associated BSR
6175L–ATARM–28-Jul-11
CONTROL
CONTROL
OUTPUT
OUTPUT
INPUT
INPUT
Cells