SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 32

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SAM9XE512

Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9XE512

Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
9.10
9.11
9.12
32
General-purpose Back-up Registers
Advanced Interrupt Controller
Debug Unit
AT91SAM9XE128/256/512 Preliminary
• Four 32-bit backup general-purpose registers
• Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
• Three External Sources plus the Fast Interrupt signal
• 8-level Priority Controller
• Vectoring
• Protect Mode
• Fast Forcing
• Composed of two functions
• Two-pin UART
• Debug Communication Channel Support
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
– Easy debugging by preventing automatic operations when protect modeIs are
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
– Two-pin UART
– Debug Communication Channel (DCC) support
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
– Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from
enabled
processor
Generator
the ARM Processor’s ICE Interface
6254C–ATARM–22-Jan-10

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