AD9467 Analog Devices, AD9467 Datasheet - Page 19

• Manufacturer Part Number: AD9467
• Description: 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9467

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,2 V p-p,2.5V p-p
• Adc Architecture: Pipelined,Subranging
• Pkg Type: CSP

THEORY OF OPERATION
The AD9467 architecture consists of an input-buffered pipe-
lined ADC that consists of a 3-bit first stage, a 4-bit second
stage, followed by four 3-bit stages and a final 3-bit flash. Each
stage provides sufficient overlap to correct for flash errors in
the preceding stage.
The input buffer provides a linear high input impedance (for
ease of drive) and reduces the kick-back from the ADC. The
buffer is optimized for high linearity, low noise, and low power.
The quantized outputs from each stage are combined into a final
16-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate with a new input
sample while the remaining stages operate with preceding samples.
Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9467 is a differential buffer. For best
dynamic performance, the source impedances driving VIN+
and VIN− should be matched such that common-mode settling
errors are symmetrical. The analog input is optimized to provide
superior wideband performance and requires that the analog
inputs be driven differentially. SNR and SINAD performance
degrades significantly if the analog input is driven with a single-
ended signal.
In either case, a small resistor in series with each input can help
reduce the peak transient current injected from the output stage
of the driving source. In addition, low Q inductors or ferrite beads
can be placed on each leg of the input to reduce high differential
capacitance at the analog inputs and, therefore, achieve the
maximum bandwidth of the ADC. Such use of low Q inductors
or ferrite beads is required when driving the converter front end at
high IF frequencies. Either a shunt capacitor or two single-ended
capacitors can be placed on the inputs to provide a matching
passive network. This ultimately creates a low-pass filter at the
input to limit unwanted broadband noise. See the
Application Note, the
Application Note, and the Analog Dialogue article
Coupled Front-End for Wideband A/D
April 2005) for more information. In general, the precise values
depend on the application.
Data Sheet
AN-827
Application Note, the
Converters” (Volume 39,
AN-742
“Transformer-
AN-935
Rev. C | Page 19 of 32
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the default
case of the AD9467, the largest input span available is 2.5 V p-p.
For other input full-scale options, see the Full-Scale and Reference
Options section.
SFDR Optimization—Buffer Current Adjustment
Using Register 36 and Register 107, the buffer currents can be
changed as a percentage to optimize the SFDR over various
input frequencies and bandwidths of interest. As the input
buffer currents are set, this does change the amount of current
required by AVDD2. However, the current consumption is
small in comparison to the overall currents required by this
supply. The current specifications listed in Table 1 incorporate
this variation. For a complete list of buffer current settings, see
Table 13 for more details.
The following buffer current settings reflect the performance
that can be achieved using the input networks as described in
Figure 51 and Figure 52. These curves describe the percentages
used to obtain data sheet typical specifications for both the
250 MSPS and 200 MSPS parts. For example, when using IFs
from 150 MHz to 250 MHz, 160% is actually the average of the
entire buffer current. Therefore, both Register 36 and Register 107
need to be set to 160%.
AD9467BCPZ-250 buffer current settings:
•
•
•
DC to 150 MHz at 80% (default setting)
150 MHz to 250 MHz at 160%
250 MHz and higher at 210%
100
98
96
94
92
90
88
86
84
82
80
Figure 49. Buffer Current Sweeps, 2.5 V p-p, AD9467-250
0
50
ANALOG INPUT FREQUENCY (MHz)
100
150
200
80%
160%
210%
250
AD9467
300