AD9467 Analog Devices, AD9467 Datasheet - Page 23

• Manufacturer Part Number: AD9467
• Description: 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9467

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,2 V p-p,2.5V p-p
• Adc Architecture: Pipelined,Subranging
• Pkg Type: CSP

Power Dissipation and Power-Down Mode
As shown in Figure 62, the power dissipated by the AD9467 is
proportional to its sample rate. The output power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
By asserting the power-down option via the SPI register map
(0x08[1:0]), the AD9467 is placed into power-down mode. In
this state, the ADC typically dissipates 5 mW. During power-down,
the LVDS output drivers are placed in a high impedance state.
In power-down mode, low power dissipation is achieved by
shutting down the internal reference, reference buffer, digital
output, and biasing networks. The device requires approx-
imately 100 ms to restore full operation.
See the Memory Map section for more details on using these
features.
Data Sheet
0.6
0.5
0.4
0.3
0.2
0.1
0.6
0.5
0.4
0.3
0.2
0.1
0
0
Figure 62. Supply Current vs. f
Figure 63. Supply Current vs. f
210
100 110 120 130 140 150 160 170 180 190 200 210 220
215
TOTAL POWER
I
I
I
AVDD1
AVDD2
DRVDD
220
TOTAL POWER
I
I
I
AVDD1
AVDD2
DRVDD
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
225
230
SAMPLE
SAMPLE
for f
for f
235
IN
IN
= 5 MHz, AD9467-200
= 5 MHz, AD9467-250
240
245
250
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.2
1.1
1.0
0.9
0.8
0.7
0.6
Rev. C | Page 23 of 32
Power Supplies
To achieve the best dynamic performance of the AD9467, it is
recommended that each power supply pin be decoupled as
closely to the package as possible with 0.1 μF, X7R or X5R type
decoupling capacitors. For optimum performance, all supplies
should be at typical values or slightly higher to accommodate
elevated temperature drifts, which depend on the application.
Full-Scale and Reference Options
The analog inputs support both an input full scale of 2.5 V p-p
(default) and 2.0 V p-p differentially. Choosing one full-scale
input range over the other presents some trade-offs to the user.
Using an input full scale of 2.5 V p-p yields the best SNR
performance. If system trade-offs require improved SFDR
performance, then a 2.0 V p-p input full scale should be used.
However, in this mode, SNR degrades by roughly 2 dB. Other
input full-scale ranges are available for use between 2.0 V p-p
and 2.5 V p-p. See Register 18 in Table 13 and the Memory Map
section for details.
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve gain matching
when using multiple ADCs.
The internal reference can be disabled via the SPI, allowing the
use of an external reference. See the Memory Map section for
more details. The external reference is loaded by the input of an
internal buffer amplifier having 3 pF of capacitance to ground.
There is also a 1 kΩ internal resistor in series with the input of
that buffer. The external reference must be limited to a nominal
1.25 V for an input full-scale swing of 2.5 V p-p. Additional
capacitance may be necessary to keep this pin quiet depending
on the external reference used.
When not using the XVREF pin, it can be tied to ground
directly or through a 0.1 μF decoupling capacitor. However,
keep this pin quiet regardless.
Digital Outputs and Timing
The AD9467 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. The LVDS driver current is
derived on chip and sets the output current at each output equal
to a nominal 3.0 mA. A 100 Ω differential termination resistor
placed at the LVDS receiver inputs results in a nominal 300 mV
swing at the receiver.
The AD9467 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
recommended that the trace length be no longer than 18 inches
and that the differential output traces be kept close together and
at equal lengths. An example of the DCO and data with proper
trace length and position is shown in Figure 64.
AD9467