AD9467 Analog Devices, AD9467 Datasheet - Page 31

• Manufacturer Part Number: AD9467
• Description: 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9467

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,2 V p-p,2.5V p-p
• Adc Architecture: Pipelined,Subranging
• Pkg Type: CSP

Power and Ground Recommendations
When connecting power to the AD9467, it is recommended
that three separate supplies be used: one for analog AVDD1 and
AVDD3 (1.8 V), one for analog AVDD2 (3.3 V), and one for
digital output drivers DRVDD (1.8 V). If only one 1.8 V supply
is available, it should be routed to AVDD1 and AVDD3 first and
then tapped off and isolated with a ferrite bead or a filter choke
preceded by decoupling capacitors for the DRVDD. The user
can employ several different decoupling capacitors to cover
both high and low frequencies. These should be located close to
the point of entry at the PC board level and close to the parts,
with minimal trace lengths.
A single PC board ground plane should be sufficient when
using the AD9467. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance can be easily achieved.
Data Sheet
Rev. C | Page 31 of 32
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9467. An
exposed continuous copper plane on the PCB should be con-
nected to the AD9467 exposed paddle, Pin 0. The copper plane
should have several vias to achieve the lowest possible resistive
thermal path for heat dissipation to flow through the bottom of
the PCB. These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
only guarantees one tie point. See Figure 69 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP).
SILKSCREEN PARTITION
PIN 1 INDICATOR
Figure 69. Typical PCB Layout
AN-772
Application Note,
AD9467