AD9641 Analog Devices, AD9641 Datasheet - Page 24

• Manufacturer Part Number: AD9641
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9641

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9641
Figure 67 shows an example of the digital output (default) data
eye and a time interval error (TIE) jitter histogram.
Additional SPI options allow the user to further increase the output
driver voltage swing of all four outputs to drive longer trace lengths
(see Address 0x15 in Table 17). Even though this produces sharper
rise and fall times on the data edges and is less prone to bit errors,
the power dissipation of the DRVDD supply increases when this
option is used. See the Memory Map section for more details.
The format of the output data is twos complement, by default.
Table 12 provides an example of this output coding format.
To change the output data format to offset binary or Gray code,
see the Memory Map section (Address 0x14 in Table 17).
Table 12. Digital Output Coding
Code
8191
0
−1
−8192
–200
–400
–600
600
400
200
0
–200
–400
400
200
–300
EYE: TRANSITION BITS
OFFSET: –0.002
UIS: 8000; 1239996, TOTAL: 48000; 7439996
0
–600
EYE: TRANSITION BITS
OFFSET: –0.004
UIS: 8000; 639999, TOTAL: 8000; 639999
–200
HEIGHT1: EYE DIAGRAM
–400
HEIGHT1: EYE DIAGRAM
–100
–200
TIME (ps)
(VIN+) − (VIN−), Input Span = 1.75 V p-p (V)
+0.875
0.00
−0.000107
−0.875
Figure 68. AD9641-155 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations
Figure 67. AD9641-80 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations
TIME (ps)
0
0
100
200
200
400
300
600
1
–
–
1
400k
350k
300k
250k
200k
150k
100k
25,000
20,000
15,000
10,000
50k
5000
0
305
0
610
310
615
PERIOD1: HISTOGRAM
Rev. B | Page 24 of 36
PERIOD1: HISTOGRAM
315
620
TIME (ps)
320
TIME (ps)
625
325
630
The lowest typical clock rate is 40 MSPS. For clock rates slower
than 60 MSPS, Bit 3 should be set to 0 in the PLL control register
(Address 0x21 in Table 17). This option sets the PLL loop band-
width to use clock rates between 40 MSPS and 60 MSPS.
Setting Bit 2 in the output mode register (Address 0x14) allows
the user to invert the digital samples from their nominal state.
As shown in Figure 63, the MSB is transmitted first in the data
output serial stream.
330
Digital Output Twos Complement ([D13:D0])
01 1111 1111 1111
00 0000 0000 0000
11 1111 1111 1111
10 0000 0000 0000
635
335
4
+
–
4
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
–10
–12
–14
10
–10
–12
–14
–2
–4
–6
–8
–0.5
0
–2
–4
–6
–8
–0.5
0
WIDTH@BER1: BATHTUB
WIDTH@BER1: BATHTUB
0.781
ULS
0
0.75
ULS
0
Data Sheet
0.5
+
0.5
3
–
3