AD9641 Analog Devices, AD9641 Datasheet - Page 6

• Manufacturer Part Number: AD9641
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9641

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9641
Parameter
LOGIC INPUT/OUTPUT (SDIO)
DIGITAL OUTPUTS
1
2
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
TERMINATION CHARACTERISTICS
OUT-OF-RANGE RECOVERY TIME
1
2
Pull up.
Pull down.
Conversion rate is the clock rate after the divider.
Wake-up time is defined as the time required to return to normal operation from power-down mode.
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Data Output Period or UI (Unit Interval)
Data Output Duty Cycle
Data Valid Time
PLL Lock Time (t
Wake Up Time (Standby)
Wake Up Time (Power-Down)
Random Jitter at 1.6 Gbps
Random Jitter at 3.1 Gbps
Output Rise/Fall Time
Differential Termination Resistance
Logic Compliance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
Input Clock Rate
Conversion Rate
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Pipeline Delay (Latency)
Data Rate (NRZ)
Deterministic Jitter
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-by-8 Mode
LOCK
1
A
)
)
OS
CH
)
)
1
OD
2
J
)
)
CLK
)
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Rev. B | Page 6 of 36
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
40
12.5
3.75
5.95
0.8
23
AD9641-80
Typ
6.25
6.25
0.78
0.125
1/(20 × f
50
0.8
4
5
2.5
1.6
40
9.5
50
100
2
Min
1.22
0
−10
38
0.6
0.75
CLK
)
Max
640
80
8.75
6.55
24
Typ
CMOS
26
5
CML
0.8
DRVDD/2
Min
23
40
6.45
1.935
3.065
0.8
AD9641-155
Typ
4
2.5
50
2
3.225
3.225
0.78
0.125
1/(20 × f
50
0.75
5
3.1
40
5.2
100
Max
2.1
0.6
+10
128
1.1
1.05
CLK
)
Max
155
24
640
4.515
3.385
Data Sheet
Unit
V
V
μA
μA
kΩ
pF
V
V
Unit
MHz
MSPS
ns
ns
ns
ns
ns
ps rms
sec
%
UI
μs
μs
ms
CLK cycles
Gbps
ps
ps rms
ps rms
ps
Ω
CLK cycles