AD9641 Analog Devices, AD9641 Datasheet - Page 28

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AD9641

Manufacturer Part Number
AD9641
Description
14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
Manufacturer
Analog Devices
Datasheet

Specifications of AD9641

Resolution (bits)
14bit
# Chan
1
Sample Rate
80MSPS
Interface
Ser
Analog Input Type
Diff-Bip
Ain Range
1.75 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP
AD9641
HARDWARE INTERFACE
The pins described in Table 15 comprise the physical interface
between the user programming device and the serial port of
the AD9641. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the
controller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the
tioning at the converter inputs during critical sampling periods.
AD9641
to prevent these signals from transi-
AN-812
Application Note, Micro-
Rev. B | Page 28 of 36
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the
via SPI. The AD9641 part-specific features are described in detail in
the Reading the Memory Map Register Table section.
Table 16. Features Accessible Using the SPI
Feature Name
Mode
Clock
Offset
Test I/O
Full Scale
JESD204A
AN-877
Application Note, Interfacing to High Speed ADCs
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS, set the
clock divider, set the clock divider phase, and
enable the sync
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set the input full-scale
voltage
Allows user to configure the JESD204A output
Data Sheet

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