AD9963 Analog Devices, AD9963 Datasheet - Page 31

• Manufacturer Part Number: AD9963
• Description: 10-/12-Bit, Low Power, Broadband MxFE
• Manufacturer: Analog Devices

Specifications of AD9963

• Resolution (bits): 12bit
• Throughput Rate: 100MSPS
• # Chan: 2
• Supply V: Multi(+1.8Anlg, +1.8Dig),Multi(+1.8Anlg, +3.3Dig) ,Single(+1.8),Single(+3.3)
• Sample Rate: 100MSPS
• Adc Bits X #adcs-speed: 12x2-100 MHz
• Dac Bits X #dacs-clkspeed: 12x2-170 MHz
• Pkg Type: CSP
• Primary Application: Broadband Wireless

Register Name
Clock Mode
I DAC Gain Ctrl 0
I DAC Gain Ctrl 1
I DAC Gain Ctrl 2
Q DAC Gain Ctrl 0
Q DAC Gain Ctrl 1
Q DAC Gain Ctrl 2
REFIO Adjust
Register
Address
0x66
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
Bit(s)
3:2
1:0
7
6
5
4
3
2
1:0
7:6
5:0
7:6
5:0
7:6
5:0
7:6
5:0
7:6
5:0
7:6
5:0
7:6
5:0
Parameter
TRXCLK_DRV
TXCLK_DRV
TXI_DCLK
TXQ_DCLK
Unused
RXI_DCLK
RXQ_DCLK
DCS_BP
ADCDIV[1:0]
Unused
IGAIN1[5:0]
Unused
IGAIN2[5:0]
Unused
IRSET[5:0]
Unused
QGAIN1[5:0]
Unused
QGAIN2[5:0]
Unused
QRSET[5:0]
Unused
REFIO_ADJ[5:0]
Rev. 0 | Page 31 of 60
Function
Controls the drive strength of the TRXCLK pin.
00: 4 mA output drive.
01: 8 mA output drive.
10: 12 mA output drive.
11: not valid.
Controls the drive strength of the TXCLK pin.
00: 4 mA output drive.
01: 8 mA output drive.
10: 12 mA output drive.
11: not valid.
1: disables internal clock to I DAC.
1: disables internal clock to Q DAC.
1: disables internal clock to I ADC.
1: disables internal clock to Q ADC.
1: disables duty cycle stabilizer block.
00: selects divide by 1. Bypasses internal divider block for RXCLK.
01: selects divide by 1. Bypasses internal divider block for RXCLK.
10: selects divide by 2.
11: selects divide by 4.
Linear in dB adjustment of the full-scale current of IDAC. Provides an
adjustment range of approximately ±6 dB in 0.25 dB steps. See Figure 57
for details.
Linear adjustment of the full-scale current of I DAC. Provides an
adjustment range of approximately ±2.5% in 0.08% steps. See Figure 55
for details.
Linear adjustment of the full-scale current of I DAC. Provides an
adjustment range of approximately ±20% in 0.625% steps. See Figure 55
for details.
Linear in dB adjustment of the full-scale current of Q DAC. Provides an
adjustment range of approximately ±6 dB in 0.25 dB steps. See Figure 56
for details.
Linear adjustment of the full-scale current of Q DAC. Provides an
adjustment range of approximately ±2.5% in 0.08% steps. See Figure 57
for details.
Linear adjustment of the full-scale current of Q DAC. Provides an
adjustment range of approximately ±20% in 0.625% steps. See Figure 55
for details.
Adjusts the on-chip reference voltage and output at REFIO. The transmit
DAC full-scale currents and the auxiliary DAC full-scale voltages are
proportional to the REFIO voltage. The approximate REFIO output
voltage by code is:
000000: V
000001: V
…
011111: V
REF
REF
REF
= 1.0 V.
= 1.00625 V.
= 1.19375 V.
AD9961/AD9963