AD7192 Analog Devices, AD7192 Datasheet - Page 22

• Manufacturer Part Number: AD7192
• Description: 4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7192

• Resolution (bits): 24bit
• # Chan: 4
• Sample Rate: 4.8kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip,SE-Uni
• Ain Range: ± (Vref/Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7192
Table 19. Configuration Register Bit Designations
Bit Location
CON23
CON22, CON21
CON20
CON19 to CON16
CON15 to CON8
CON7
CON6
CON5
CON4
CON3
CON2 to CON0
Bit Name
CHOP
0
REFSEL
0
CH7 to CH0
BURN
REFDET
0
BUF
U/B
G2 to G0
Chop enable bit. When the CHOP bit is cleared, chop is disabled. When the CHOP bit is set, chop is
enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed.
However, this increases the conversion time and settling time of the ADC. For example, when FS = 96
decimal and the sinc
settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word of
96 decimal and the sinc
However, at low gains, periodic calibrations may be required to remove the offset and offset drift.
These bits must be programmed with a Logic 0 for correct operation.
Reference select bits. The reference source for the ADC is selected using these bits.
REFSEL
0
1
These bits must be programmed with a Logic 0 for correct operation.
Channel select bits. These bits are used to select which channels are enabled on the AD7192 (see Table 20).
Several channels can be selected, and the AD7192 automatically sequences them. The conversion on
each channel requires the complete settling time. When performing calibrations or when accessing the
calibration registers, only one channel can be selected.
When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When BURN = 0, the
burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and
when chop is disabled.
Enables the reference detect function. When set, the NOREF bit in the status register indicates when the
external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference
detect circuitry operates only when the ADC is active.
This bit must be programmed with a Logic 0 for correct operation.
Enables the buffer on the analog inputs. If cleared, the analog inputs are unbuffered, lowering the
power consumption of the device. If this bit is set, the analog inputs are buffered, allowing the user to
place source impedances on the front end without contributing gain errors to the system. With the
buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above
AV
must be limited to 250 mV within the power supply rails.
Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar
operation is selected.
Gain select bits. These bits are written by the user to select the ADC input range as follows:
G2
0
0
0
0
1
1
1
1
Description
DD
. When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin
G1
0
0
1
1
0
0
1
1
4
0
Reference Voltage
External reference applied between REFIN1(+) and REFIN1(−).
External reference applied between the P1/REFIN2(+) and P0/REFIN2(−) pins.
G0
1
0
1
0
1
0
1
filter is selected, the conversion time with chop enabled equals 80 ms and the
4
filter selected, the conversion time is 20 ms and the settling time is 80 ms.
Rev. A | Page 22 of 40
Gain
1
Reserved
Reserved
8
16
32
64
128
ADC Input Range (5 V Reference)
±5 V
±625 mV
±312.5 mV
±156.2 mV
±78.125 mV
±39.06 mV