AD7946 Analog Devices, AD7946 Datasheet - Page 12

• Manufacturer Part Number: AD7946
• Manufacturer: Analog Devices

Specifications of AD7946

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7946
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7946 is a fast, low power, single-supply, precise 14-bit
ADC using a successive approximation architecture.
The AD7946 can convert 500,000 samples per second (500 kSPS)
and powers down between conversions. When operating at
100 SPS, for example, it consumes 3.3 μW typically, ideal for
battery-powered applications.
The AD7946 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7946 is specified from 4.5 V to 5.5 V and can be
interfaced to any of the 1.8 V to 5 V digital logic family. It is
housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that
combines space savings and allows flexible configurations.
It is pin-for-pin compatible with the 16-bit ADC AD7686.
CONVERTER OPERATION
The AD7946 is a successive approximation ADC based on a
charge redistribution DAC. Figure 23 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 14 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, the terminals of the array that are
tied to the comparator’s input are connected to GND via SW+
and SW−. All independent switches are connected to the analog
inputs. Thus, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is complete and the CNV input goes high,
a conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary weighted voltage steps (REF/2, REF/4 … REF/16,384).
GND
REF
IN+
IN–
8192C
8192C
MSB
MSB
4096C
4096C
Figure 23. ADC Simplified Schematic
4C
4C
Rev. A | Page 12 of 24
2C
2C
C
C
The control logic toggles these switches, starting with the MSB,
in order to bring the comparator back into a balanced condition.
After completing this process, the part returns to the acquisition
phase, and the control logic generates the ADC output code and
a BUSY signal indicator.
Because the AD7946 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Transfer Functions
The ideal transfer characteristic for the AD7946 is shown in
Figure 24 and Table 7.
Table 7. Output Codes and Ideal Input Voltages
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
1 This is also the code for an overranged analog input (V
2
This is also the code for an underranged analog input (V
C
C
000...010
000...001
000...000
111...101
111...111
111...110
LSB
LSB
–FSR + 0.5 LSB
–FSR
SW+
SW–
Figure 24. ADC Ideal Transfer Function
COMP
Analog Input
REF = 5 V
4.999695 V
2.500305 V
2.5 V
2.499695 V
305.2 μV
0 V
–FSR + 1 LSB
SWITCHES CONTROL
CONTROL
LOGIC
CNV
ANALOG INPUT
Digital Output Code Hexa
3FFF
2001
2000
1FFF
0001
0000
+FSR – 1.5 LSB
BUSY
OUTPUT CODE
1
2
IN+
− V
+FSR – 1 LSB
IN+
IN−
− V
above REF − V
IN−
below V
GND
GND
).
).